Module stm32h7xx_hal::pac::rtc::cr [−][src]
RTC control register
Structs
| ADD1H_W | Write proxy for field |
| ALRAE_W | Write proxy for field |
| ALRAIE_W | Write proxy for field |
| ALRBE_W | Write proxy for field |
| ALRBIE_W | Write proxy for field |
| BKP_W | Write proxy for field |
| BYPSHAD_W | Write proxy for field |
| COE_W | Write proxy for field |
| COSEL_W | Write proxy for field |
| FMT_W | Write proxy for field |
| ITSE_W | Write proxy for field |
| OSEL_W | Write proxy for field |
| POL_W | Write proxy for field |
| REFCKON_W | Write proxy for field |
| SUB1H_W | Write proxy for field |
| TSEDGE_W | Write proxy for field |
| TSE_W | Write proxy for field |
| TSIE_W | Write proxy for field |
| WUCKSEL_W | Write proxy for field |
| WUTE_W | Write proxy for field |
| WUTIE_W | Write proxy for field |
Enums
| ADD1H_AW | Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. |
| ALRAE_A | Alarm A enable |
| ALRAIE_A | Alarm A interrupt enable |
| ALRBE_A | Alarm B enable |
| ALRBIE_A | Alarm B interrupt enable |
| BKP_A | Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. |
| BYPSHAD_A | Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. |
| COE_A | Calibration output enable This bit enables the RTC_CALIB output |
| COSEL_A | Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section24.3.15: Calibration clock output |
| FMT_A | Hour format |
| ITSE_A | timestamp on internal event enable |
| OSEL_A | Output selection These bits are used to select the flag to be routed to RTC_ALARM output |
| POL_A | Output polarity This bit is used to configure the polarity of RTC_ALARM output |
| REFCKON_A | RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF. |
| SUB1H_AW | Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. |
| TSEDGE_A | Time-stamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. |
| TSE_A | timestamp enable |
| TSIE_A | Time-stamp interrupt enable |
| WUCKSEL_A | Wakeup clock selection |
| WUTE_A | Wakeup timer enable |
| WUTIE_A | Wakeup timer interrupt enable |
Type Definitions
| ALRAE_R | Reader of field |
| ALRAIE_R | Reader of field |
| ALRBE_R | Reader of field |
| ALRBIE_R | Reader of field |
| BKP_R | Reader of field |
| BYPSHAD_R | Reader of field |
| COE_R | Reader of field |
| COSEL_R | Reader of field |
| FMT_R | Reader of field |
| ITSE_R | Reader of field |
| OSEL_R | Reader of field |
| POL_R | Reader of field |
| R | Reader of register CR |
| REFCKON_R | Reader of field |
| TSEDGE_R | Reader of field |
| TSE_R | Reader of field |
| TSIE_R | Reader of field |
| W | Writer for register CR |
| WUCKSEL_R | Reader of field |
| WUTE_R | Reader of field |
| WUTIE_R | Reader of field |