Module stm32h7xx_hal::pac::i2c1::timeoutr [−][src]
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
Structs
TEXTEN_W | Write proxy for field |
TIDLE_W | Write proxy for field |
TIMEOUTA_W | Write proxy for field |
TIMEOUTB_W | Write proxy for field |
TIMOUTEN_W | Write proxy for field |
Enums
TEXTEN_A | Extended clock timeout enable |
TIDLE_A | Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0. |
TIMOUTEN_A | Clock timeout enable |
Type Definitions
R | Reader of register TIMEOUTR |
TEXTEN_R | Reader of field |
TIDLE_R | Reader of field |
TIMEOUTA_R | Reader of field |
TIMEOUTB_R | Reader of field |
TIMOUTEN_R | Reader of field |
W | Writer for register TIMEOUTR |