Module stm32h7xx_hal::pac::i2c1::oar2 [−][src]
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
Structs
| OA2EN_W | Write proxy for field |
| OA2MSK_W | Write proxy for field |
| OA2_W | Write proxy for field |
Enums
| OA2EN_A | Own Address 2 enable |
| OA2MSK_A | Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. |
Type Definitions
| OA2EN_R | Reader of field |
| OA2MSK_R | Reader of field |
| OA2_R | Reader of field |
| R | Reader of register OAR2 |
| W | Writer for register OAR2 |