Struct stm32h7xx_hal::pac::gpioa::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub moder: Reg<u32, _MODER>,
    pub otyper: Reg<u32, _OTYPER>,
    pub ospeedr: Reg<u32, _OSPEEDR>,
    pub pupdr: Reg<u32, _PUPDR>,
    pub idr: Reg<u32, _IDR>,
    pub odr: Reg<u32, _ODR>,
    pub bsrr: Reg<u32, _BSRR>,
    pub lckr: Reg<u32, _LCKR>,
    pub afrl: Reg<u32, _AFRL>,
    pub afrh: Reg<u32, _AFRH>,
}

Register block

Fields

moder: Reg<u32, _MODER>

0x00 - GPIO port mode register

otyper: Reg<u32, _OTYPER>

0x04 - GPIO port output type register

ospeedr: Reg<u32, _OSPEEDR>

0x08 - GPIO port output speed register

pupdr: Reg<u32, _PUPDR>

0x0c - GPIO port pull-up/pull-down register

idr: Reg<u32, _IDR>

0x10 - GPIO port input data register

odr: Reg<u32, _ODR>

0x14 - GPIO port output data register

bsrr: Reg<u32, _BSRR>

0x18 - GPIO port bit set/reset register

lckr: Reg<u32, _LCKR>

0x1c - This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

afrl: Reg<u32, _AFRL>

0x20 - GPIO alternate function low register

afrh: Reg<u32, _AFRH>

0x24 - GPIO alternate function high register