Module stm32h7xx_hal::pac::fmc::sr

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

Structs

IFEN_W	Write proxy for field IFEN
IFS_W	Write proxy for field IFS
ILEN_W	Write proxy for field ILEN
ILS_W	Write proxy for field ILS
IREN_W	Write proxy for field IREN
IRS_W	Write proxy for field IRS

Type Definitions

FEMPT_R	Reader of field FEMPT
IFEN_R	Reader of field IFEN
IFS_R	Reader of field IFS
ILEN_R	Reader of field ILEN
ILS_R	Reader of field ILS
IREN_R	Reader of field IREN
IRS_R	Reader of field IRS
R	Reader of register SR
W	Writer for register SR