Module stm32h7xx_hal::pac::bdma::isr

DMA interrupt status register

Enums

GIF1_A	Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF1_A	Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF1_A	Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF1_A	Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

Type Definitions

GIF1_R	Reader of field GIF1
GIF2_A	Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF2_R	Reader of field GIF2
GIF3_A	Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF3_R	Reader of field GIF3
GIF4_A	Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF4_R	Reader of field GIF4
GIF5_A	Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF5_R	Reader of field GIF5
GIF6_A	Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF6_R	Reader of field GIF6
GIF7_A	Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF7_R	Reader of field GIF7
GIF8_A	Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF8_R	Reader of field GIF8
HTIF1_R	Reader of field HTIF1
HTIF2_A	Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF2_R	Reader of field HTIF2
HTIF3_A	Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF3_R	Reader of field HTIF3
HTIF4_A	Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF4_R	Reader of field HTIF4
HTIF5_A	Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF5_R	Reader of field HTIF5
HTIF6_A	Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF6_R	Reader of field HTIF6
HTIF7_A	Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF7_R	Reader of field HTIF7
HTIF8_A	Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF8_R	Reader of field HTIF8
R	Reader of register ISR
TCIF1_R	Reader of field TCIF1
TCIF2_A	Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF2_R	Reader of field TCIF2
TCIF3_A	Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF3_R	Reader of field TCIF3
TCIF4_A	Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF4_R	Reader of field TCIF4
TCIF5_A	Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF5_R	Reader of field TCIF5
TCIF6_A	Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF6_R	Reader of field TCIF6
TCIF7_A	Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF7_R	Reader of field TCIF7
TCIF8_A	Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF8_R	Reader of field TCIF8
TEIF1_R	Reader of field TEIF1
TEIF2_A	Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF2_R	Reader of field TEIF2
TEIF3_A	Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF3_R	Reader of field TEIF3
TEIF4_A	Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF4_R	Reader of field TEIF4
TEIF5_A	Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF5_R	Reader of field TEIF5
TEIF6_A	Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF6_R	Reader of field TEIF6
TEIF7_A	Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF7_R	Reader of field TEIF7
TEIF8_A	Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF8_R	Reader of field TEIF8