Module stm32h7xx_hal::device::sai4::ch::im [−][src]
Interrupt mask register 2
Structs
| AFSDETIE_W | Write proxy for field |
| CNRDYIE_W | Write proxy for field |
| FREQIE_W | Write proxy for field |
| LFSDETIE_W | Write proxy for field |
| MUTEDETIE_W | Write proxy for field |
| OVRUDRIE_W | Write proxy for field |
| WCKCFGIE_W | Write proxy for field |
Enums
| AFSDETIE_A | Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. |
| CNRDYIE_A | Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. |
| FREQIE_A | FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, |
| LFSDETIE_A | Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. |
| MUTEDETIE_A | Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. |
| OVRUDRIE_A | Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. |
| WCKCFGIE_A | Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. |
Type Definitions
| AFSDETIE_R | Reader of field |
| CNRDYIE_R | Reader of field |
| FREQIE_R | Reader of field |
| LFSDETIE_R | Reader of field |
| MUTEDETIE_R | Reader of field |
| OVRUDRIE_R | Reader of field |
| R | Reader of register IM |
| W | Writer for register IM |
| WCKCFGIE_R | Reader of field |