Module stm32h7xx_hal::device::pwr::cr3 [−][src]
Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.
Structs
| BYPASS_W | Write proxy for field |
| LDOEN_W | Write proxy for field |
| SCUEN_W | Write proxy for field |
| USB33DEN_W | Write proxy for field |
| USBREGEN_W | Write proxy for field |
| VBE_W | Write proxy for field |
| VBRS_W | Write proxy for field |
Type Definitions
| BYPASS_R | Reader of field |
| LDOEN_R | Reader of field |
| R | Reader of register CR3 |
| SCUEN_R | Reader of field |
| USB33DEN_R | Reader of field |
| USB33RDY_R | Reader of field |
| USBREGEN_R | Reader of field |
| VBE_R | Reader of field |
| VBRS_R | Reader of field |
| W | Writer for register CR3 |