Module stm32h7xx_hal::device::pwr::cr2 [−][src]
This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.
Structs
| BREN_W | Write proxy for field |
| MONEN_W | Write proxy for field |
Type Definitions
| BREN_R | Reader of field |
| BRRDY_R | Reader of field |
| MONEN_R | Reader of field |
| R | Reader of register CR2 |
| TEMPH_R | Reader of field |
| TEMPL_R | Reader of field |
| VBATH_R | Reader of field |
| VBATL_R | Reader of field |
| W | Writer for register CR2 |