Struct stm32h7xx_hal::stm32::gpioa::lckr::W

source ·

pub struct W(/* private fields */);

Expand description

Register LCKR writer

Implementations§

source §

impl W

source

pub fn lck0(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 0>

Bit 0 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck1(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 1>

Bit 1 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck2(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 2>

Bit 2 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck3(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 3>

Bit 3 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck4(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 4>

Bit 4 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck5(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 5>

Bit 5 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck6(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 6>

Bit 6 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck7(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 7>

Bit 7 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck8(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 8>

Bit 8 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck9(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 9>

Bit 9 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck10(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 10>

Bit 10 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck11(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 11>

Bit 11 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck12(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 12>

Bit 12 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck13(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 13>

Bit 13 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck14(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 14>

Bit 14 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lck15(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCK0_A, BitM, 15>

Bit 15 - Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0.

source

pub fn lckk(&mut self) -> BitWriterRaw<'_, u32, LCKR_SPEC, LCKK_A, BitM, 16>

Bit 16 - Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset.

source