Module stm32h7xx_hal::dma

Direct Memory Access

This module implements Memory To Memory, Peripheral To Memory and Memory to Peripheral transfers. Double buffering is supported only for Peripheral To Memory and Memory to Peripheral transfers.

Controllers

STM32H7 parts contain several DMA controllers with differing capabilities. The choice of DMA controller is a trade-off between capabilities, performance and power usage. This module implements methods for all the available DMA controllers.

Whilst not strictly enforced, each peripheral is typically associated with a particular controller. These links are documented in the ‘Block interconnect’ section of the Reference Manual. In most cases, a peripheral will be used with its associated DMA controller.

The following table summarizes the available DMA controllers

Controller	Accessible Memories	Peripheral TargetAddress Implementations	Double Buffering Supported ?	Number of DMA Streams	Initialization Method
MDMA	All	QUADSPI, ..	No	16	Transfer::init_master
DMA1	AXISRAM, SRAM1/2/3/4	all others 1	Yes	8	Transfer::init
DMA2	AXISRAM, SRAM1/2/3/4	all others 1	Yes	8	Transfer::init
BDMA	SRAM4 2	LPUART1, SPI6, I2C4, SAI4	Yes	8	Transfer::init

Safety

Transfer::init is only implemented for valid combinations of peripheral-stream-channel-direction, providing compile time checking.

The module uses fences to prevent the compiler and CPU from reording certain operations. This is particularly important since the Cortex-M7 core is otherwise capable of reordering accesses between normal and device memory. See ARM DAI 0321A, Section 3.2 which discusses the use of DMB instructions in DMA controller configuration.

Usage

Starting a transfer

Transfer are started using the start method. This method accepts a closure with a mutable reference to the peripheral for this transfer. For Peripheral to Memory or Memory to Peripheral transfers to/from some peripherals, this closure is used to complete the initialisation of the peripheral. If the Peripheral requires initialisation before enabling the DMA stream, you should do this before creating the transfer or start the transfer using one of the methods available to continue transfers.

Calling start() multiple times on the same transfer is undefined behaviour. Instead, the transfer should be continued.

Continuing a transfer

For DMA controllers that support Double Buffering, the following methods are available to continue transfers:

• next_transfer
• next_transfer_with
• next_dbm_transfer_with

Examples

• Memory to Memory Transfer
• I2C Read using Basic DMA (BDMA)
• Serial Transmit using DMA
• SPI using DMA
• SPI using DMA and the RTIC framework
• Memory to Memory Transfer using Master DMA(MDMA)
• Using MDMA with multiple beats per burst

Credits

Adapted from https://github.com/stm32-rs/stm32f4xx-hal/blob/master/src/dma/mod.rs

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1. TargetAddress is not yet implemented for many peripherals ↩

2. On 7B3/7A3/7B0 parts there are two BDMA controllers. BDMA1 can access SRAM1/2 whilst BDMA2 is limited to SRAM4. For these parts this HAL only supports BDMA2. ↩

Modules

• bdma
  BDMA
• config
  Contains types related to DMA configuration.
• dma
  DMA1 and DMA2
• mdma
  Master DMA
• traits
  Traits for DMA types

Structs

• ConstDBTransfer
  Marker type for a transfer with a constant source and backed by a DoubleBufferedStream
• DBTransfer
  Marker type for a transfer with a mutable source and backed by a DoubleBufferedStream
• MasterTransfer
  Marker type for a transfer with a mutable source and backed by a MasterStream
• MemoryToMemory
  DMA from one memory location to another memory location.
• MemoryToPeripheral
  DMA from a memory location to a peripheral.
• PeripheralToMemory
  DMA from a peripheral to a memory location.
• Transfer
  DMA Transfer.

Enums

• CurrentBuffer
  Which DMA buffer is in use.
• DMAError
  Errors.
• DmaDirection
  Possible DMA’s directions.
• FifoLevel
  How full the DMA stream’s fifo is.