Struct stm32h7x3::dma2d::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub dma2d_cr: DMA2D_CR, pub dma2d_isr: DMA2D_ISR, pub dma2d_ifcr: DMA2D_IFCR, pub dma2d_fgmar: DMA2D_FGMAR, pub dma2d_fgor: DMA2D_FGOR, pub dma2d_bgmar: DMA2D_BGMAR, pub dma2d_bgor: DMA2D_BGOR, pub dma2d_fgpfccr: DMA2D_FGPFCCR, pub dma2d_fgcolr: DMA2D_FGCOLR, pub dma2d_bgpfccr: DMA2D_BGPFCCR, pub dma2d_bgcolr: DMA2D_BGCOLR, pub dma2d_fgcmar: DMA2D_FGCMAR, pub dma2d_bgcmar: DMA2D_BGCMAR, pub dma2d_opfccr: DMA2D_OPFCCR, pub dma2d_ocolr: DMA2D_OCOLR, pub dma2d_omar: DMA2D_OMAR, pub dma2d_oor: DMA2D_OOR, pub dma2d_nlr: DMA2D_NLR, pub dma2d_lwr: DMA2D_LWR, pub dma2d_amtcr: DMA2D_AMTCR, }
Register block
Fields
dma2d_cr: DMA2D_CR
0x00 - DMA2D control register
dma2d_isr: DMA2D_ISR
0x04 - DMA2D Interrupt Status Register
dma2d_ifcr: DMA2D_IFCR
0x08 - DMA2D interrupt flag clear register
dma2d_fgmar: DMA2D_FGMAR
0x0c - DMA2D foreground memory address register
dma2d_fgor: DMA2D_FGOR
0x10 - DMA2D foreground offset register
dma2d_bgmar: DMA2D_BGMAR
0x14 - DMA2D background memory address register
dma2d_bgor: DMA2D_BGOR
0x18 - DMA2D background offset register
dma2d_fgpfccr: DMA2D_FGPFCCR
0x1c - DMA2D foreground PFC control register
dma2d_fgcolr: DMA2D_FGCOLR
0x20 - DMA2D foreground color register
dma2d_bgpfccr: DMA2D_BGPFCCR
0x24 - DMA2D background PFC control register
dma2d_bgcolr: DMA2D_BGCOLR
0x28 - DMA2D background color register
dma2d_fgcmar: DMA2D_FGCMAR
0x2c - DMA2D foreground CLUT memory address register
dma2d_bgcmar: DMA2D_BGCMAR
0x30 - DMA2D background CLUT memory address register
dma2d_opfccr: DMA2D_OPFCCR
0x34 - DMA2D output PFC control register
dma2d_ocolr: DMA2D_OCOLR
0x38 - DMA2D output color register
dma2d_omar: DMA2D_OMAR
0x3c - DMA2D output memory address register
dma2d_oor: DMA2D_OOR
0x40 - DMA2D output offset register
dma2d_nlr: DMA2D_NLR
0x44 - DMA2D number of line register
dma2d_lwr: DMA2D_LWR
0x48 - DMA2D line watermark register
dma2d_amtcr: DMA2D_AMTCR
0x4c - DMA2D AXI master timer configuration register