Expand description
This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected.
Structs
This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected.
Register CFGR reader
Register CFGR writer
Type Definitions
Field FELIM reader - Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0]
bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation.
Field FELIM writer - Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0]
bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation.
Field RELOAD reader - Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior.
Field RELOAD writer - Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior.
Field SYNCDIV reader - SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal.
Field SYNCDIV writer - SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal.
Field SYNCPOL reader - SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source.
Field SYNCPOL writer - SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source.
Field SYNCSRC reader - SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal.
Field SYNCSRC writer - SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal.