1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
#[doc = "Register `C1_APB4ENR` reader"]
pub struct R(crate::R<C1_APB4ENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<C1_APB4ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<C1_APB4ENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<C1_APB4ENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `C1_APB4ENR` writer"]
pub struct W(crate::W<C1_APB4ENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<C1_APB4ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<C1_APB4ENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<C1_APB4ENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "SYSCFG peripheral clock enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYSCFGEN_A {
#[doc = "0: The selected clock is disabled"]
Disabled = 0,
#[doc = "1: The selected clock is enabled"]
Enabled = 1,
}
impl From<SYSCFGEN_A> for bool {
#[inline(always)]
fn from(variant: SYSCFGEN_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SYSCFGEN` reader - SYSCFG peripheral clock enable"]
pub type SYSCFGEN_R = crate::BitReader<SYSCFGEN_A>;
impl SYSCFGEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> SYSCFGEN_A {
match self.bits {
false => SYSCFGEN_A::Disabled,
true => SYSCFGEN_A::Enabled,
}
}
#[doc = "Checks if the value of the field is `Disabled`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SYSCFGEN_A::Disabled
}
#[doc = "Checks if the value of the field is `Enabled`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SYSCFGEN_A::Enabled
}
}
#[doc = "Field `SYSCFGEN` writer - SYSCFG peripheral clock enable"]
pub type SYSCFGEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, C1_APB4ENR_SPEC, SYSCFGEN_A, O>;
impl<'a, const O: u8> SYSCFGEN_W<'a, O> {
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::Disabled)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::Enabled)
}
}
#[doc = "LPUART1 Peripheral Clocks Enable"]
pub use SYSCFGEN_A as LPUART1EN_A;
#[doc = "SPI6 Peripheral Clocks Enable"]
pub use SYSCFGEN_A as SPI6EN_A;
#[doc = "I2C4 Peripheral Clocks Enable"]
pub use SYSCFGEN_A as I2C4EN_A;
#[doc = "LPTIM2 Peripheral Clocks Enable"]
pub use SYSCFGEN_A as LPTIM2EN_A;
#[doc = "LPTIM3 Peripheral Clocks Enable"]
pub use SYSCFGEN_A as LPTIM3EN_A;
#[doc = "LPTIM4 Peripheral Clocks Enable"]
pub use SYSCFGEN_A as LPTIM4EN_A;
#[doc = "LPTIM5 Peripheral Clocks Enable"]
pub use SYSCFGEN_A as LPTIM5EN_A;
#[doc = "COMP1/2 peripheral clock enable"]
pub use SYSCFGEN_A as COMP12EN_A;
#[doc = "VREF peripheral clock enable"]
pub use SYSCFGEN_A as VREFEN_A;
#[doc = "RTC APB Clock Enable"]
pub use SYSCFGEN_A as RTCAPBEN_A;
#[doc = "SAI4 Peripheral Clocks Enable"]
pub use SYSCFGEN_A as SAI4EN_A;
#[doc = "Field `LPUART1EN` reader - LPUART1 Peripheral Clocks Enable"]
pub use SYSCFGEN_R as LPUART1EN_R;
#[doc = "Field `SPI6EN` reader - SPI6 Peripheral Clocks Enable"]
pub use SYSCFGEN_R as SPI6EN_R;
#[doc = "Field `I2C4EN` reader - I2C4 Peripheral Clocks Enable"]
pub use SYSCFGEN_R as I2C4EN_R;
#[doc = "Field `LPTIM2EN` reader - LPTIM2 Peripheral Clocks Enable"]
pub use SYSCFGEN_R as LPTIM2EN_R;
#[doc = "Field `LPTIM3EN` reader - LPTIM3 Peripheral Clocks Enable"]
pub use SYSCFGEN_R as LPTIM3EN_R;
#[doc = "Field `LPTIM4EN` reader - LPTIM4 Peripheral Clocks Enable"]
pub use SYSCFGEN_R as LPTIM4EN_R;
#[doc = "Field `LPTIM5EN` reader - LPTIM5 Peripheral Clocks Enable"]
pub use SYSCFGEN_R as LPTIM5EN_R;
#[doc = "Field `COMP12EN` reader - COMP1/2 peripheral clock enable"]
pub use SYSCFGEN_R as COMP12EN_R;
#[doc = "Field `VREFEN` reader - VREF peripheral clock enable"]
pub use SYSCFGEN_R as VREFEN_R;
#[doc = "Field `RTCAPBEN` reader - RTC APB Clock Enable"]
pub use SYSCFGEN_R as RTCAPBEN_R;
#[doc = "Field `SAI4EN` reader - SAI4 Peripheral Clocks Enable"]
pub use SYSCFGEN_R as SAI4EN_R;
#[doc = "Field `LPUART1EN` writer - LPUART1 Peripheral Clocks Enable"]
pub use SYSCFGEN_W as LPUART1EN_W;
#[doc = "Field `SPI6EN` writer - SPI6 Peripheral Clocks Enable"]
pub use SYSCFGEN_W as SPI6EN_W;
#[doc = "Field `I2C4EN` writer - I2C4 Peripheral Clocks Enable"]
pub use SYSCFGEN_W as I2C4EN_W;
#[doc = "Field `LPTIM2EN` writer - LPTIM2 Peripheral Clocks Enable"]
pub use SYSCFGEN_W as LPTIM2EN_W;
#[doc = "Field `LPTIM3EN` writer - LPTIM3 Peripheral Clocks Enable"]
pub use SYSCFGEN_W as LPTIM3EN_W;
#[doc = "Field `LPTIM4EN` writer - LPTIM4 Peripheral Clocks Enable"]
pub use SYSCFGEN_W as LPTIM4EN_W;
#[doc = "Field `LPTIM5EN` writer - LPTIM5 Peripheral Clocks Enable"]
pub use SYSCFGEN_W as LPTIM5EN_W;
#[doc = "Field `COMP12EN` writer - COMP1/2 peripheral clock enable"]
pub use SYSCFGEN_W as COMP12EN_W;
#[doc = "Field `VREFEN` writer - VREF peripheral clock enable"]
pub use SYSCFGEN_W as VREFEN_W;
#[doc = "Field `RTCAPBEN` writer - RTC APB Clock Enable"]
pub use SYSCFGEN_W as RTCAPBEN_W;
#[doc = "Field `SAI4EN` writer - SAI4 Peripheral Clocks Enable"]
pub use SYSCFGEN_W as SAI4EN_W;
impl R {
#[doc = "Bit 1 - SYSCFG peripheral clock enable"]
#[inline(always)]
pub fn syscfgen(&self) -> SYSCFGEN_R {
SYSCFGEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3 - LPUART1 Peripheral Clocks Enable"]
#[inline(always)]
pub fn lpuart1en(&self) -> LPUART1EN_R {
LPUART1EN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 5 - SPI6 Peripheral Clocks Enable"]
#[inline(always)]
pub fn spi6en(&self) -> SPI6EN_R {
SPI6EN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7 - I2C4 Peripheral Clocks Enable"]
#[inline(always)]
pub fn i2c4en(&self) -> I2C4EN_R {
I2C4EN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 9 - LPTIM2 Peripheral Clocks Enable"]
#[inline(always)]
pub fn lptim2en(&self) -> LPTIM2EN_R {
LPTIM2EN_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - LPTIM3 Peripheral Clocks Enable"]
#[inline(always)]
pub fn lptim3en(&self) -> LPTIM3EN_R {
LPTIM3EN_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - LPTIM4 Peripheral Clocks Enable"]
#[inline(always)]
pub fn lptim4en(&self) -> LPTIM4EN_R {
LPTIM4EN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - LPTIM5 Peripheral Clocks Enable"]
#[inline(always)]
pub fn lptim5en(&self) -> LPTIM5EN_R {
LPTIM5EN_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 14 - COMP1/2 peripheral clock enable"]
#[inline(always)]
pub fn comp12en(&self) -> COMP12EN_R {
COMP12EN_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - VREF peripheral clock enable"]
#[inline(always)]
pub fn vrefen(&self) -> VREFEN_R {
VREFEN_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - RTC APB Clock Enable"]
#[inline(always)]
pub fn rtcapben(&self) -> RTCAPBEN_R {
RTCAPBEN_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 21 - SAI4 Peripheral Clocks Enable"]
#[inline(always)]
pub fn sai4en(&self) -> SAI4EN_R {
SAI4EN_R::new(((self.bits >> 21) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - SYSCFG peripheral clock enable"]
#[inline(always)]
pub fn syscfgen(&mut self) -> SYSCFGEN_W<1> {
SYSCFGEN_W::new(self)
}
#[doc = "Bit 3 - LPUART1 Peripheral Clocks Enable"]
#[inline(always)]
pub fn lpuart1en(&mut self) -> LPUART1EN_W<3> {
LPUART1EN_W::new(self)
}
#[doc = "Bit 5 - SPI6 Peripheral Clocks Enable"]
#[inline(always)]
pub fn spi6en(&mut self) -> SPI6EN_W<5> {
SPI6EN_W::new(self)
}
#[doc = "Bit 7 - I2C4 Peripheral Clocks Enable"]
#[inline(always)]
pub fn i2c4en(&mut self) -> I2C4EN_W<7> {
I2C4EN_W::new(self)
}
#[doc = "Bit 9 - LPTIM2 Peripheral Clocks Enable"]
#[inline(always)]
pub fn lptim2en(&mut self) -> LPTIM2EN_W<9> {
LPTIM2EN_W::new(self)
}
#[doc = "Bit 10 - LPTIM3 Peripheral Clocks Enable"]
#[inline(always)]
pub fn lptim3en(&mut self) -> LPTIM3EN_W<10> {
LPTIM3EN_W::new(self)
}
#[doc = "Bit 11 - LPTIM4 Peripheral Clocks Enable"]
#[inline(always)]
pub fn lptim4en(&mut self) -> LPTIM4EN_W<11> {
LPTIM4EN_W::new(self)
}
#[doc = "Bit 12 - LPTIM5 Peripheral Clocks Enable"]
#[inline(always)]
pub fn lptim5en(&mut self) -> LPTIM5EN_W<12> {
LPTIM5EN_W::new(self)
}
#[doc = "Bit 14 - COMP1/2 peripheral clock enable"]
#[inline(always)]
pub fn comp12en(&mut self) -> COMP12EN_W<14> {
COMP12EN_W::new(self)
}
#[doc = "Bit 15 - VREF peripheral clock enable"]
#[inline(always)]
pub fn vrefen(&mut self) -> VREFEN_W<15> {
VREFEN_W::new(self)
}
#[doc = "Bit 16 - RTC APB Clock Enable"]
#[inline(always)]
pub fn rtcapben(&mut self) -> RTCAPBEN_W<16> {
RTCAPBEN_W::new(self)
}
#[doc = "Bit 21 - SAI4 Peripheral Clocks Enable"]
#[inline(always)]
pub fn sai4en(&mut self) -> SAI4EN_W<21> {
SAI4EN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RCC APB4 Clock Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c1_apb4enr](index.html) module"]
pub struct C1_APB4ENR_SPEC;
impl crate::RegisterSpec for C1_APB4ENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [c1_apb4enr::R](R) reader structure"]
impl crate::Readable for C1_APB4ENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [c1_apb4enr::W](W) writer structure"]
impl crate::Writable for C1_APB4ENR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets C1_APB4ENR to value 0"]
impl crate::Resettable for C1_APB4ENR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}
