#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::I2SCFGR {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `MCKOE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MCKOER {
#[doc = "Master clock output disabled"]
DISABLED,
#[doc = "Master clock output enabled"]
ENABLED,
}
impl MCKOER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
MCKOER::DISABLED => false,
MCKOER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> MCKOER {
match value {
false => MCKOER::DISABLED,
true => MCKOER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MCKOER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == MCKOER::ENABLED
}
}
#[doc = "Values that can be written to the field `MCKOE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MCKOEW {
#[doc = "Master clock output disabled"]
DISABLED,
#[doc = "Master clock output enabled"]
ENABLED,
}
impl MCKOEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
MCKOEW::DISABLED => false,
MCKOEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _MCKOEW<'a> {
w: &'a mut W,
}
impl<'a> _MCKOEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MCKOEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Master clock output disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(MCKOEW::DISABLED)
}
#[doc = "Master clock output enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(MCKOEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 25);
self.w.bits |= ((value as u32) & 0x01) << 25;
self.w
}
}
#[doc = "Possible values of the field `ODD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ODDR {
#[doc = "Real divider value is I2SDIV*2"]
EVEN,
#[doc = "Real divider value is I2SDIV*2 + 1"]
ODD,
}
impl ODDR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
ODDR::EVEN => false,
ODDR::ODD => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> ODDR {
match value {
false => ODDR::EVEN,
true => ODDR::ODD,
}
}
#[doc = "Checks if the value of the field is `EVEN`"]
#[inline(always)]
pub fn is_even(&self) -> bool {
*self == ODDR::EVEN
}
#[doc = "Checks if the value of the field is `ODD`"]
#[inline(always)]
pub fn is_odd(&self) -> bool {
*self == ODDR::ODD
}
}
#[doc = "Values that can be written to the field `ODD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ODDW {
#[doc = "Real divider value is I2SDIV*2"]
EVEN,
#[doc = "Real divider value is I2SDIV*2 + 1"]
ODD,
}
impl ODDW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
ODDW::EVEN => false,
ODDW::ODD => true,
}
}
}
#[doc = r"Proxy"]
pub struct _ODDW<'a> {
w: &'a mut W,
}
impl<'a> _ODDW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ODDW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Real divider value is I2SDIV*2"]
#[inline(always)]
pub fn even(self) -> &'a mut W {
self.variant(ODDW::EVEN)
}
#[doc = "Real divider value is I2SDIV*2 + 1"]
#[inline(always)]
pub fn odd(self) -> &'a mut W {
self.variant(ODDW::ODD)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 24);
self.w.bits |= ((value as u32) & 0x01) << 24;
self.w
}
}
#[doc = r"Value of the field"]
pub struct I2SDIVR {
bits: u8,
}
impl I2SDIVR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _I2SDIVW<'a> {
w: &'a mut W,
}
impl<'a> _I2SDIVW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0xff << 16);
self.w.bits |= ((value as u32) & 0xff) << 16;
self.w
}
}
#[doc = "Possible values of the field `DATFMT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DATFMTR {
#[doc = "The data inside RXDR and TXDR are right aligned"]
RIGHTALIGNED,
#[doc = "The data inside RXDR and TXDR are left aligned"]
LEFTALIGNED,
}
impl DATFMTR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
DATFMTR::RIGHTALIGNED => false,
DATFMTR::LEFTALIGNED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> DATFMTR {
match value {
false => DATFMTR::RIGHTALIGNED,
true => DATFMTR::LEFTALIGNED,
}
}
#[doc = "Checks if the value of the field is `RIGHTALIGNED`"]
#[inline(always)]
pub fn is_right_aligned(&self) -> bool {
*self == DATFMTR::RIGHTALIGNED
}
#[doc = "Checks if the value of the field is `LEFTALIGNED`"]
#[inline(always)]
pub fn is_left_aligned(&self) -> bool {
*self == DATFMTR::LEFTALIGNED
}
}
#[doc = "Values that can be written to the field `DATFMT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DATFMTW {
#[doc = "The data inside RXDR and TXDR are right aligned"]
RIGHTALIGNED,
#[doc = "The data inside RXDR and TXDR are left aligned"]
LEFTALIGNED,
}
impl DATFMTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
DATFMTW::RIGHTALIGNED => false,
DATFMTW::LEFTALIGNED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _DATFMTW<'a> {
w: &'a mut W,
}
impl<'a> _DATFMTW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DATFMTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The data inside RXDR and TXDR are right aligned"]
#[inline(always)]
pub fn right_aligned(self) -> &'a mut W {
self.variant(DATFMTW::RIGHTALIGNED)
}
#[doc = "The data inside RXDR and TXDR are left aligned"]
#[inline(always)]
pub fn left_aligned(self) -> &'a mut W {
self.variant(DATFMTW::LEFTALIGNED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 14);
self.w.bits |= ((value as u32) & 0x01) << 14;
self.w
}
}
#[doc = "Possible values of the field `WSINV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WSINVR {
#[doc = "Word select inversion disabled"]
DISABLED,
#[doc = "Word select inversion enabled"]
ENABLED,
}
impl WSINVR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
WSINVR::DISABLED => false,
WSINVR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> WSINVR {
match value {
false => WSINVR::DISABLED,
true => WSINVR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == WSINVR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == WSINVR::ENABLED
}
}
#[doc = "Values that can be written to the field `WSINV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WSINVW {
#[doc = "Word select inversion disabled"]
DISABLED,
#[doc = "Word select inversion enabled"]
ENABLED,
}
impl WSINVW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
WSINVW::DISABLED => false,
WSINVW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _WSINVW<'a> {
w: &'a mut W,
}
impl<'a> _WSINVW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: WSINVW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Word select inversion disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(WSINVW::DISABLED)
}
#[doc = "Word select inversion enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(WSINVW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 13);
self.w.bits |= ((value as u32) & 0x01) << 13;
self.w
}
}
#[doc = "Possible values of the field `FIXCH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIXCHR {
#[doc = "The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)"]
NOTFIXED,
#[doc = "The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)"]
FIXED,
}
impl FIXCHR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
FIXCHR::NOTFIXED => false,
FIXCHR::FIXED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> FIXCHR {
match value {
false => FIXCHR::NOTFIXED,
true => FIXCHR::FIXED,
}
}
#[doc = "Checks if the value of the field is `NOTFIXED`"]
#[inline(always)]
pub fn is_not_fixed(&self) -> bool {
*self == FIXCHR::NOTFIXED
}
#[doc = "Checks if the value of the field is `FIXED`"]
#[inline(always)]
pub fn is_fixed(&self) -> bool {
*self == FIXCHR::FIXED
}
}
#[doc = "Values that can be written to the field `FIXCH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIXCHW {
#[doc = "The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)"]
NOTFIXED,
#[doc = "The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)"]
FIXED,
}
impl FIXCHW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
FIXCHW::NOTFIXED => false,
FIXCHW::FIXED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _FIXCHW<'a> {
w: &'a mut W,
}
impl<'a> _FIXCHW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FIXCHW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)"]
#[inline(always)]
pub fn not_fixed(self) -> &'a mut W {
self.variant(FIXCHW::NOTFIXED)
}
#[doc = "The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)"]
#[inline(always)]
pub fn fixed(self) -> &'a mut W {
self.variant(FIXCHW::FIXED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 12);
self.w.bits |= ((value as u32) & 0x01) << 12;
self.w
}
}
#[doc = "Possible values of the field `CKPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CKPOLR {
#[doc = "Signals are sampled on rising and changed on falling clock edges"]
SAMPLEONRISING,
#[doc = "Signals are sampled on falling and changed on rising clock edges"]
SAMPLEONFALLING,
}
impl CKPOLR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
CKPOLR::SAMPLEONRISING => false,
CKPOLR::SAMPLEONFALLING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> CKPOLR {
match value {
false => CKPOLR::SAMPLEONRISING,
true => CKPOLR::SAMPLEONFALLING,
}
}
#[doc = "Checks if the value of the field is `SAMPLEONRISING`"]
#[inline(always)]
pub fn is_sample_on_rising(&self) -> bool {
*self == CKPOLR::SAMPLEONRISING
}
#[doc = "Checks if the value of the field is `SAMPLEONFALLING`"]
#[inline(always)]
pub fn is_sample_on_falling(&self) -> bool {
*self == CKPOLR::SAMPLEONFALLING
}
}
#[doc = "Values that can be written to the field `CKPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CKPOLW {
#[doc = "Signals are sampled on rising and changed on falling clock edges"]
SAMPLEONRISING,
#[doc = "Signals are sampled on falling and changed on rising clock edges"]
SAMPLEONFALLING,
}
impl CKPOLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CKPOLW::SAMPLEONRISING => false,
CKPOLW::SAMPLEONFALLING => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CKPOLW<'a> {
w: &'a mut W,
}
impl<'a> _CKPOLW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CKPOLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Signals are sampled on rising and changed on falling clock edges"]
#[inline(always)]
pub fn sample_on_rising(self) -> &'a mut W {
self.variant(CKPOLW::SAMPLEONRISING)
}
#[doc = "Signals are sampled on falling and changed on rising clock edges"]
#[inline(always)]
pub fn sample_on_falling(self) -> &'a mut W {
self.variant(CKPOLW::SAMPLEONFALLING)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 11);
self.w.bits |= ((value as u32) & 0x01) << 11;
self.w
}
}
#[doc = "Possible values of the field `CHLEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHLENR {
#[doc = "16 bit per channel"]
BITS16,
#[doc = "32 bit per channel"]
BITS32,
}
impl CHLENR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
CHLENR::BITS16 => false,
CHLENR::BITS32 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> CHLENR {
match value {
false => CHLENR::BITS16,
true => CHLENR::BITS32,
}
}
#[doc = "Checks if the value of the field is `BITS16`"]
#[inline(always)]
pub fn is_bits16(&self) -> bool {
*self == CHLENR::BITS16
}
#[doc = "Checks if the value of the field is `BITS32`"]
#[inline(always)]
pub fn is_bits32(&self) -> bool {
*self == CHLENR::BITS32
}
}
#[doc = "Values that can be written to the field `CHLEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CHLENW {
#[doc = "16 bit per channel"]
BITS16,
#[doc = "32 bit per channel"]
BITS32,
}
impl CHLENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CHLENW::BITS16 => false,
CHLENW::BITS32 => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CHLENW<'a> {
w: &'a mut W,
}
impl<'a> _CHLENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CHLENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "16 bit per channel"]
#[inline(always)]
pub fn bits16(self) -> &'a mut W {
self.variant(CHLENW::BITS16)
}
#[doc = "32 bit per channel"]
#[inline(always)]
pub fn bits32(self) -> &'a mut W {
self.variant(CHLENW::BITS32)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 10);
self.w.bits |= ((value as u32) & 0x01) << 10;
self.w
}
}
#[doc = "Possible values of the field `DATLEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DATLENR {
#[doc = "16 bit data length"]
BITS16,
#[doc = "24 bit data length"]
BITS24,
#[doc = "32 bit data length"]
BITS32,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl DATLENR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
DATLENR::BITS16 => 0,
DATLENR::BITS24 => 0x01,
DATLENR::BITS32 => 0x02,
DATLENR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> DATLENR {
match value {
0 => DATLENR::BITS16,
1 => DATLENR::BITS24,
2 => DATLENR::BITS32,
i => DATLENR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `BITS16`"]
#[inline(always)]
pub fn is_bits16(&self) -> bool {
*self == DATLENR::BITS16
}
#[doc = "Checks if the value of the field is `BITS24`"]
#[inline(always)]
pub fn is_bits24(&self) -> bool {
*self == DATLENR::BITS24
}
#[doc = "Checks if the value of the field is `BITS32`"]
#[inline(always)]
pub fn is_bits32(&self) -> bool {
*self == DATLENR::BITS32
}
}
#[doc = "Values that can be written to the field `DATLEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DATLENW {
#[doc = "16 bit data length"]
BITS16,
#[doc = "24 bit data length"]
BITS24,
#[doc = "32 bit data length"]
BITS32,
}
impl DATLENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
DATLENW::BITS16 => 0,
DATLENW::BITS24 => 1,
DATLENW::BITS32 => 2,
}
}
}
#[doc = r"Proxy"]
pub struct _DATLENW<'a> {
w: &'a mut W,
}
impl<'a> _DATLENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DATLENW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "16 bit data length"]
#[inline(always)]
pub fn bits16(self) -> &'a mut W {
self.variant(DATLENW::BITS16)
}
#[doc = "24 bit data length"]
#[inline(always)]
pub fn bits24(self) -> &'a mut W {
self.variant(DATLENW::BITS24)
}
#[doc = "32 bit data length"]
#[inline(always)]
pub fn bits32(self) -> &'a mut W {
self.variant(DATLENW::BITS32)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 8);
self.w.bits |= ((value as u32) & 0x03) << 8;
self.w
}
}
#[doc = "Possible values of the field `PCMSYNC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCMSYNCR {
#[doc = "Short PCM frame synchronization"]
SHORT,
#[doc = "Long PCM frame synchronization"]
LONG,
}
impl PCMSYNCR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
PCMSYNCR::SHORT => false,
PCMSYNCR::LONG => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> PCMSYNCR {
match value {
false => PCMSYNCR::SHORT,
true => PCMSYNCR::LONG,
}
}
#[doc = "Checks if the value of the field is `SHORT`"]
#[inline(always)]
pub fn is_short(&self) -> bool {
*self == PCMSYNCR::SHORT
}
#[doc = "Checks if the value of the field is `LONG`"]
#[inline(always)]
pub fn is_long(&self) -> bool {
*self == PCMSYNCR::LONG
}
}
#[doc = "Values that can be written to the field `PCMSYNC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCMSYNCW {
#[doc = "Short PCM frame synchronization"]
SHORT,
#[doc = "Long PCM frame synchronization"]
LONG,
}
impl PCMSYNCW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
PCMSYNCW::SHORT => false,
PCMSYNCW::LONG => true,
}
}
}
#[doc = r"Proxy"]
pub struct _PCMSYNCW<'a> {
w: &'a mut W,
}
impl<'a> _PCMSYNCW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PCMSYNCW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Short PCM frame synchronization"]
#[inline(always)]
pub fn short(self) -> &'a mut W {
self.variant(PCMSYNCW::SHORT)
}
#[doc = "Long PCM frame synchronization"]
#[inline(always)]
pub fn long(self) -> &'a mut W {
self.variant(PCMSYNCW::LONG)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 7);
self.w.bits |= ((value as u32) & 0x01) << 7;
self.w
}
}
#[doc = "Possible values of the field `I2SSTD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2SSTDR {
#[doc = "I2S Philips standard"]
PHILIPS,
#[doc = "MSB/left justified standard"]
LEFTALIGNED,
#[doc = "LSB/right justified standard"]
RIGHTALIGNED,
#[doc = "PCM standard"]
PCM,
}
impl I2SSTDR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
I2SSTDR::PHILIPS => 0,
I2SSTDR::LEFTALIGNED => 0x01,
I2SSTDR::RIGHTALIGNED => 0x02,
I2SSTDR::PCM => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> I2SSTDR {
match value {
0 => I2SSTDR::PHILIPS,
1 => I2SSTDR::LEFTALIGNED,
2 => I2SSTDR::RIGHTALIGNED,
3 => I2SSTDR::PCM,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PHILIPS`"]
#[inline(always)]
pub fn is_philips(&self) -> bool {
*self == I2SSTDR::PHILIPS
}
#[doc = "Checks if the value of the field is `LEFTALIGNED`"]
#[inline(always)]
pub fn is_left_aligned(&self) -> bool {
*self == I2SSTDR::LEFTALIGNED
}
#[doc = "Checks if the value of the field is `RIGHTALIGNED`"]
#[inline(always)]
pub fn is_right_aligned(&self) -> bool {
*self == I2SSTDR::RIGHTALIGNED
}
#[doc = "Checks if the value of the field is `PCM`"]
#[inline(always)]
pub fn is_pcm(&self) -> bool {
*self == I2SSTDR::PCM
}
}
#[doc = "Values that can be written to the field `I2SSTD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2SSTDW {
#[doc = "I2S Philips standard"]
PHILIPS,
#[doc = "MSB/left justified standard"]
LEFTALIGNED,
#[doc = "LSB/right justified standard"]
RIGHTALIGNED,
#[doc = "PCM standard"]
PCM,
}
impl I2SSTDW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
I2SSTDW::PHILIPS => 0,
I2SSTDW::LEFTALIGNED => 1,
I2SSTDW::RIGHTALIGNED => 2,
I2SSTDW::PCM => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _I2SSTDW<'a> {
w: &'a mut W,
}
impl<'a> _I2SSTDW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2SSTDW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "I2S Philips standard"]
#[inline(always)]
pub fn philips(self) -> &'a mut W {
self.variant(I2SSTDW::PHILIPS)
}
#[doc = "MSB/left justified standard"]
#[inline(always)]
pub fn left_aligned(self) -> &'a mut W {
self.variant(I2SSTDW::LEFTALIGNED)
}
#[doc = "LSB/right justified standard"]
#[inline(always)]
pub fn right_aligned(self) -> &'a mut W {
self.variant(I2SSTDW::RIGHTALIGNED)
}
#[doc = "PCM standard"]
#[inline(always)]
pub fn pcm(self) -> &'a mut W {
self.variant(I2SSTDW::PCM)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 4);
self.w.bits |= ((value as u32) & 0x03) << 4;
self.w
}
}
#[doc = "Possible values of the field `I2SCFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2SCFGR {
#[doc = "Slave, transmit"]
SLAVETRANSMIT,
#[doc = "Slave, recteive"]
SLAVERECEIVE,
#[doc = "Master, transmit"]
MASTERTRANSMIT,
#[doc = "Master, receive"]
MASTERRECEIVE,
#[doc = "Slave, full duplex"]
SLAVEFULLDUPLEX,
#[doc = "Master, full duplex"]
MASTERFULLDUPLEX,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl I2SCFGR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
I2SCFGR::SLAVETRANSMIT => 0,
I2SCFGR::SLAVERECEIVE => 0x01,
I2SCFGR::MASTERTRANSMIT => 0x02,
I2SCFGR::MASTERRECEIVE => 0x03,
I2SCFGR::SLAVEFULLDUPLEX => 0x04,
I2SCFGR::MASTERFULLDUPLEX => 0x05,
I2SCFGR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> I2SCFGR {
match value {
0 => I2SCFGR::SLAVETRANSMIT,
1 => I2SCFGR::SLAVERECEIVE,
2 => I2SCFGR::MASTERTRANSMIT,
3 => I2SCFGR::MASTERRECEIVE,
4 => I2SCFGR::SLAVEFULLDUPLEX,
5 => I2SCFGR::MASTERFULLDUPLEX,
i => I2SCFGR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `SLAVETRANSMIT`"]
#[inline(always)]
pub fn is_slave_transmit(&self) -> bool {
*self == I2SCFGR::SLAVETRANSMIT
}
#[doc = "Checks if the value of the field is `SLAVERECEIVE`"]
#[inline(always)]
pub fn is_slave_receive(&self) -> bool {
*self == I2SCFGR::SLAVERECEIVE
}
#[doc = "Checks if the value of the field is `MASTERTRANSMIT`"]
#[inline(always)]
pub fn is_master_transmit(&self) -> bool {
*self == I2SCFGR::MASTERTRANSMIT
}
#[doc = "Checks if the value of the field is `MASTERRECEIVE`"]
#[inline(always)]
pub fn is_master_receive(&self) -> bool {
*self == I2SCFGR::MASTERRECEIVE
}
#[doc = "Checks if the value of the field is `SLAVEFULLDUPLEX`"]
#[inline(always)]
pub fn is_slave_full_duplex(&self) -> bool {
*self == I2SCFGR::SLAVEFULLDUPLEX
}
#[doc = "Checks if the value of the field is `MASTERFULLDUPLEX`"]
#[inline(always)]
pub fn is_master_full_duplex(&self) -> bool {
*self == I2SCFGR::MASTERFULLDUPLEX
}
}
#[doc = "Values that can be written to the field `I2SCFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2SCFGW {
#[doc = "Slave, transmit"]
SLAVETRANSMIT,
#[doc = "Slave, recteive"]
SLAVERECEIVE,
#[doc = "Master, transmit"]
MASTERTRANSMIT,
#[doc = "Master, receive"]
MASTERRECEIVE,
#[doc = "Slave, full duplex"]
SLAVEFULLDUPLEX,
#[doc = "Master, full duplex"]
MASTERFULLDUPLEX,
}
impl I2SCFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
I2SCFGW::SLAVETRANSMIT => 0,
I2SCFGW::SLAVERECEIVE => 1,
I2SCFGW::MASTERTRANSMIT => 2,
I2SCFGW::MASTERRECEIVE => 3,
I2SCFGW::SLAVEFULLDUPLEX => 4,
I2SCFGW::MASTERFULLDUPLEX => 5,
}
}
}
#[doc = r"Proxy"]
pub struct _I2SCFGW<'a> {
w: &'a mut W,
}
impl<'a> _I2SCFGW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2SCFGW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Slave, transmit"]
#[inline(always)]
pub fn slave_transmit(self) -> &'a mut W {
self.variant(I2SCFGW::SLAVETRANSMIT)
}
#[doc = "Slave, recteive"]
#[inline(always)]
pub fn slave_receive(self) -> &'a mut W {
self.variant(I2SCFGW::SLAVERECEIVE)
}
#[doc = "Master, transmit"]
#[inline(always)]
pub fn master_transmit(self) -> &'a mut W {
self.variant(I2SCFGW::MASTERTRANSMIT)
}
#[doc = "Master, receive"]
#[inline(always)]
pub fn master_receive(self) -> &'a mut W {
self.variant(I2SCFGW::MASTERRECEIVE)
}
#[doc = "Slave, full duplex"]
#[inline(always)]
pub fn slave_full_duplex(self) -> &'a mut W {
self.variant(I2SCFGW::SLAVEFULLDUPLEX)
}
#[doc = "Master, full duplex"]
#[inline(always)]
pub fn master_full_duplex(self) -> &'a mut W {
self.variant(I2SCFGW::MASTERFULLDUPLEX)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 1);
self.w.bits |= ((value as u32) & 0x07) << 1;
self.w
}
}
#[doc = "Possible values of the field `I2SMOD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2SMODR {
#[doc = "SPI mode selected"]
SPI,
#[doc = "I2S/PCM mode selected"]
I2S,
}
impl I2SMODR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
I2SMODR::SPI => false,
I2SMODR::I2S => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> I2SMODR {
match value {
false => I2SMODR::SPI,
true => I2SMODR::I2S,
}
}
#[doc = "Checks if the value of the field is `SPI`"]
#[inline(always)]
pub fn is_spi(&self) -> bool {
*self == I2SMODR::SPI
}
#[doc = "Checks if the value of the field is `I2S`"]
#[inline(always)]
pub fn is_i2s(&self) -> bool {
*self == I2SMODR::I2S
}
}
#[doc = "Values that can be written to the field `I2SMOD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2SMODW {
#[doc = "SPI mode selected"]
SPI,
#[doc = "I2S/PCM mode selected"]
I2S,
}
impl I2SMODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
I2SMODW::SPI => false,
I2SMODW::I2S => true,
}
}
}
#[doc = r"Proxy"]
pub struct _I2SMODW<'a> {
w: &'a mut W,
}
impl<'a> _I2SMODW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2SMODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SPI mode selected"]
#[inline(always)]
pub fn spi(self) -> &'a mut W {
self.variant(I2SMODW::SPI)
}
#[doc = "I2S/PCM mode selected"]
#[inline(always)]
pub fn i2s(self) -> &'a mut W {
self.variant(I2SMODW::I2S)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 0);
self.w.bits |= ((value as u32) & 0x01) << 0;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 25 - Master clock output enable"]
#[inline(always)]
pub fn mckoe(&self) -> MCKOER {
MCKOER::_from(((self.bits >> 25) & 0x01) != 0)
}
#[doc = "Bit 24 - Odd factor for the prescaler"]
#[inline(always)]
pub fn odd(&self) -> ODDR {
ODDR::_from(((self.bits >> 24) & 0x01) != 0)
}
#[doc = "Bits 16:23 - I2S linear prescaler"]
#[inline(always)]
pub fn i2sdiv(&self) -> I2SDIVR {
let bits = ((self.bits >> 16) & 0xff) as u8;
I2SDIVR { bits }
}
#[doc = "Bit 14 - Data format"]
#[inline(always)]
pub fn datfmt(&self) -> DATFMTR {
DATFMTR::_from(((self.bits >> 14) & 0x01) != 0)
}
#[doc = "Bit 13 - Fixed channel length in SLAVE"]
#[inline(always)]
pub fn wsinv(&self) -> WSINVR {
WSINVR::_from(((self.bits >> 13) & 0x01) != 0)
}
#[doc = "Bit 12 - Word select inversion"]
#[inline(always)]
pub fn fixch(&self) -> FIXCHR {
FIXCHR::_from(((self.bits >> 12) & 0x01) != 0)
}
#[doc = "Bit 11 - Serial audio clock polarity"]
#[inline(always)]
pub fn ckpol(&self) -> CKPOLR {
CKPOLR::_from(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bit 10 - Channel length (number of bits per audio channel)"]
#[inline(always)]
pub fn chlen(&self) -> CHLENR {
CHLENR::_from(((self.bits >> 10) & 0x01) != 0)
}
#[doc = "Bits 8:9 - Data length to be transferred"]
#[inline(always)]
pub fn datlen(&self) -> DATLENR {
DATLENR::_from(((self.bits >> 8) & 0x03) as u8)
}
#[doc = "Bit 7 - PCM frame synchronization"]
#[inline(always)]
pub fn pcmsync(&self) -> PCMSYNCR {
PCMSYNCR::_from(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bits 4:5 - I2S standard selection"]
#[inline(always)]
pub fn i2sstd(&self) -> I2SSTDR {
I2SSTDR::_from(((self.bits >> 4) & 0x03) as u8)
}
#[doc = "Bits 1:3 - I2S configuration mode"]
#[inline(always)]
pub fn i2scfg(&self) -> I2SCFGR {
I2SCFGR::_from(((self.bits >> 1) & 0x07) as u8)
}
#[doc = "Bit 0 - I2S mode selection"]
#[inline(always)]
pub fn i2smod(&self) -> I2SMODR {
I2SMODR::_from(((self.bits >> 0) & 0x01) != 0)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 25 - Master clock output enable"]
#[inline(always)]
pub fn mckoe(&mut self) -> _MCKOEW {
_MCKOEW { w: self }
}
#[doc = "Bit 24 - Odd factor for the prescaler"]
#[inline(always)]
pub fn odd(&mut self) -> _ODDW {
_ODDW { w: self }
}
#[doc = "Bits 16:23 - I2S linear prescaler"]
#[inline(always)]
pub fn i2sdiv(&mut self) -> _I2SDIVW {
_I2SDIVW { w: self }
}
#[doc = "Bit 14 - Data format"]
#[inline(always)]
pub fn datfmt(&mut self) -> _DATFMTW {
_DATFMTW { w: self }
}
#[doc = "Bit 13 - Fixed channel length in SLAVE"]
#[inline(always)]
pub fn wsinv(&mut self) -> _WSINVW {
_WSINVW { w: self }
}
#[doc = "Bit 12 - Word select inversion"]
#[inline(always)]
pub fn fixch(&mut self) -> _FIXCHW {
_FIXCHW { w: self }
}
#[doc = "Bit 11 - Serial audio clock polarity"]
#[inline(always)]
pub fn ckpol(&mut self) -> _CKPOLW {
_CKPOLW { w: self }
}
#[doc = "Bit 10 - Channel length (number of bits per audio channel)"]
#[inline(always)]
pub fn chlen(&mut self) -> _CHLENW {
_CHLENW { w: self }
}
#[doc = "Bits 8:9 - Data length to be transferred"]
#[inline(always)]
pub fn datlen(&mut self) -> _DATLENW {
_DATLENW { w: self }
}
#[doc = "Bit 7 - PCM frame synchronization"]
#[inline(always)]
pub fn pcmsync(&mut self) -> _PCMSYNCW {
_PCMSYNCW { w: self }
}
#[doc = "Bits 4:5 - I2S standard selection"]
#[inline(always)]
pub fn i2sstd(&mut self) -> _I2SSTDW {
_I2SSTDW { w: self }
}
#[doc = "Bits 1:3 - I2S configuration mode"]
#[inline(always)]
pub fn i2scfg(&mut self) -> _I2SCFGW {
_I2SCFGW { w: self }
}
#[doc = "Bit 0 - I2S mode selection"]
#[inline(always)]
pub fn i2smod(&mut self) -> _I2SMODW {
_I2SMODW { w: self }
}
}