#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CCR {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `DMAREQ_ID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAREQ_IDR {
#[doc = "No signal selected as request input"]
NONE,
#[doc = "Signal `dmamux1_req_gen0` selected as request input"]
DMAMUX1_REQ_GEN0,
#[doc = "Signal `dmamux1_req_gen1` selected as request input"]
DMAMUX1_REQ_GEN1,
#[doc = "Signal `dmamux1_req_gen2` selected as request input"]
DMAMUX1_REQ_GEN2,
#[doc = "Signal `dmamux1_req_gen3` selected as request input"]
DMAMUX1_REQ_GEN3,
#[doc = "Signal `dmamux1_req_gen4` selected as request input"]
DMAMUX1_REQ_GEN4,
#[doc = "Signal `dmamux1_req_gen5` selected as request input"]
DMAMUX1_REQ_GEN5,
#[doc = "Signal `dmamux1_req_gen6` selected as request input"]
DMAMUX1_REQ_GEN6,
#[doc = "Signal `dmamux1_req_gen7` selected as request input"]
DMAMUX1_REQ_GEN7,
#[doc = "Signal `adc1_dma` selected as request input"]
ADC1_DMA,
#[doc = "Signal `adc2_dma` selected as request input"]
ADC2_DMA,
#[doc = "Signal `tim1_ch1` selected as request input"]
TIM1_CH1,
#[doc = "Signal `tim1_ch2` selected as request input"]
TIM1_CH2,
#[doc = "Signal `tim1_ch3` selected as request input"]
TIM1_CH3,
#[doc = "Signal `tim1_ch4` selected as request input"]
TIM1_CH4,
#[doc = "Signal `tim1_up` selected as request input"]
TIM1_UP,
#[doc = "Signal `tim1_trig` selected as request input"]
TIM1_TRIG,
#[doc = "Signal `tim1_com` selected as request input"]
TIM1_COM,
#[doc = "Signal `tim2_ch1` selected as request input"]
TIM2_CH1,
#[doc = "Signal `tim2_ch2` selected as request input"]
TIM2_CH2,
#[doc = "Signal `tim2_ch3` selected as request input"]
TIM2_CH3,
#[doc = "Signal `tim2_ch4` selected as request input"]
TIM2_CH4,
#[doc = "Signal `tim2_up` selected as request input"]
TIM2_UP,
#[doc = "Signal `tim3_ch1` selected as request input"]
TIM3_CH1,
#[doc = "Signal `tim3_ch2` selected as request input"]
TIM3_CH2,
#[doc = "Signal `tim3_ch3` selected as request input"]
TIM3_CH3,
#[doc = "Signal `tim3_ch4` selected as request input"]
TIM3_CH4,
#[doc = "Signal `tim3_up` selected as request input"]
TIM3_UP,
#[doc = "Signal `tim3_trig` selected as request input"]
TIM3_TRIG,
#[doc = "Signal `tim4_ch1` selected as request input"]
TIM4_CH1,
#[doc = "Signal `tim4_ch2` selected as request input"]
TIM4_CH2,
#[doc = "Signal `tim4_ch3` selected as request input"]
TIM4_CH3,
#[doc = "Signal `tim4_up` selected as request input"]
TIM4_UP,
#[doc = "Signal `i2c1_rx_dma` selected as request input"]
I2C1_RX_DMA,
#[doc = "Signal `i2c1_tx_dma` selected as request input"]
I2C1_TX_DMA,
#[doc = "Signal `i2c2_rx_dma` selected as request input"]
I2C2_RX_DMA,
#[doc = "Signal `i2c2_tx_dma` selected as request input"]
I2C2_TX_DMA,
#[doc = "Signal `spi1_rx_dma` selected as request input"]
SPI1_RX_DMA,
#[doc = "Signal `spi1_tx_dma` selected as request input"]
SPI1_TX_DMA,
#[doc = "Signal `spi2_rx_dma` selected as request input"]
SPI2_RX_DMA,
#[doc = "Signal `spi2_tx_dma` selected as request input"]
SPI2_TX_DMA,
#[doc = "Signal `usart1_rx_dma` selected as request input"]
USART1_RX_DMA,
#[doc = "Signal `usart1_tx_dma` selected as request input"]
USART1_TX_DMA,
#[doc = "Signal `usart2_rx_dma` selected as request input"]
USART2_RX_DMA,
#[doc = "Signal `usart2_tx_dma` selected as request input"]
USART2_TX_DMA,
#[doc = "Signal `usart3_rx_dma` selected as request input"]
USART3_RX_DMA,
#[doc = "Signal `usart3_tx_dma` selected as request input"]
USART3_TX_DMA,
#[doc = "Signal `tim8_ch1` selected as request input"]
TIM8_CH1,
#[doc = "Signal `tim8_ch2` selected as request input"]
TIM8_CH2,
#[doc = "Signal `tim8_ch3` selected as request input"]
TIM8_CH3,
#[doc = "Signal `tim8_ch4` selected as request input"]
TIM8_CH4,
#[doc = "Signal `tim8_up` selected as request input"]
TIM8_UP,
#[doc = "Signal `tim8_trig` selected as request input"]
TIM8_TRIG,
#[doc = "Signal `tim8_com` selected as request input"]
TIM8_COM,
#[doc = "Signal `tim5_ch1` selected as request input"]
TIM5_CH1,
#[doc = "Signal `tim5_ch2` selected as request input"]
TIM5_CH2,
#[doc = "Signal `tim5_ch3` selected as request input"]
TIM5_CH3,
#[doc = "Signal `tim5_ch4` selected as request input"]
TIM5_CH4,
#[doc = "Signal `tim5_up` selected as request input"]
TIM5_UP,
#[doc = "Signal `tim5_trig` selected as request input"]
TIM5_TRIG,
#[doc = "Signal `spi3_rx_dma` selected as request input"]
SPI3_RX_DMA,
#[doc = "Signal `spi3_tx_dma` selected as request input"]
SPI3_TX_DMA,
#[doc = "Signal `uart4_rx_dma` selected as request input"]
UART4_RX_DMA,
#[doc = "Signal `uart4_tx_dma` selected as request input"]
UART4_TX_DMA,
#[doc = "Signal `uart5_rx_dma` selected as request input"]
UART5_RX_DMA,
#[doc = "Signal `uart5_tx_dma` selected as request input"]
UART5_TX_DMA,
#[doc = "Signal `dac_ch1_dma` selected as request input"]
DAC_CH1_DMA,
#[doc = "Signal `dac_ch2_dma` selected as request input"]
DAC_CH2_DMA,
#[doc = "Signal `tim6_up` selected as request input"]
TIM6_UP,
#[doc = "Signal `tim7_up` selected as request input"]
TIM7_UP,
#[doc = "Signal `usart6_rx_dma` selected as request input"]
USART6_RX_DMA,
#[doc = "Signal `usart6_tx_dma` selected as request input"]
USART6_TX_DMA,
#[doc = "Signal `i2c3_rx_dma` selected as request input"]
I2C3_RX_DMA,
#[doc = "Signal `i2c3_tx_dma` selected as request input"]
I2C3_TX_DMA,
#[doc = "Signal `dcmi_dma` selected as request input"]
DCMI_DMA,
#[doc = "Signal `cryp_in_dma` selected as request input"]
CRYP_IN_DMA,
#[doc = "Signal `cryp_out_dma` selected as request input"]
CRYP_OUT_DMA,
#[doc = "Signal `hash_in_dma` selected as request input"]
HASH_IN_DMA,
#[doc = "Signal `uart7_rx_dma` selected as request input"]
UART7_RX_DMA,
#[doc = "Signal `uart7_tx_dma` selected as request input"]
UART7_TX_DMA,
#[doc = "Signal `uart8_rx_dma` selected as request input"]
UART8_RX_DMA,
#[doc = "Signal `uart8_tx_dma` selected as request input"]
UART8_TX_DMA,
#[doc = "Signal `spi4_rx_dma` selected as request input"]
SPI4_RX_DMA,
#[doc = "Signal `spi4_tx_dma` selected as request input"]
SPI4_TX_DMA,
#[doc = "Signal `spi5_rx_dma` selected as request input"]
SPI5_RX_DMA,
#[doc = "Signal `spi5_tx_dma` selected as request input"]
SPI5_TX_DMA,
#[doc = "Signal `sai1a_dma` selected as request input"]
SAI1A_DMA,
#[doc = "Signal `sai1b_dma` selected as request input"]
SAI1B_DMA,
#[doc = "Signal `sai2a_dma` selected as request input"]
SAI2A_DMA,
#[doc = "Signal `sai2b_dma` selected as request input"]
SAI2B_DMA,
#[doc = "Signal `swpmi_rx_dma` selected as request input"]
SWPMI_RX_DMA,
#[doc = "Signal `swpmi_tx_dma` selected as request input"]
SWPMI_TX_DMA,
#[doc = "Signal `spdifrx_dat_dma` selected as request input"]
SPDIFRX_DAT_DMA,
#[doc = "Signal `spdifrx_ctrl_dma` selected as request input"]
SPDIFRX_CTRL_DMA,
#[doc = "Signal `hr_req(1)` selected as request input"]
HR_REQ1,
#[doc = "Signal `hr_req(2)` selected as request input"]
HR_REQ2,
#[doc = "Signal `hr_req(3)` selected as request input"]
HR_REQ3,
#[doc = "Signal `hr_req(4)` selected as request input"]
HR_REQ4,
#[doc = "Signal `hr_req(5)` selected as request input"]
HR_REQ5,
#[doc = "Signal `hr_req(6)` selected as request input"]
HR_REQ6,
#[doc = "Signal `dfsdm1_dma0` selected as request input"]
DFSDM1_DMA0,
#[doc = "Signal `dfsdm1_dma1` selected as request input"]
DFSDM1_DMA1,
#[doc = "Signal `dfsdm1_dma2` selected as request input"]
DFSDM1_DMA2,
#[doc = "Signal `dfsdm1_dma3` selected as request input"]
DFSDM1_DMA3,
#[doc = "Signal `tim15_ch1` selected as request input"]
TIM15_CH1,
#[doc = "Signal `tim15_up` selected as request input"]
TIM15_UP,
#[doc = "Signal `tim15_trig` selected as request input"]
TIM15_TRIG,
#[doc = "Signal `tim15_com` selected as request input"]
TIM15_COM,
#[doc = "Signal `tim16_ch1` selected as request input"]
TIM16_CH1,
#[doc = "Signal `tim16_up` selected as request input"]
TIM16_UP,
#[doc = "Signal `tim17_ch1` selected as request input"]
TIM17_CH1,
#[doc = "Signal `tim17_up` selected as request input"]
TIM17_UP,
#[doc = "Signal `sai3_a_dma` selected as request input"]
SAI3_A_DMA,
#[doc = "Signal `sai3_b_dma` selected as request input"]
SAI3_B_DMA,
#[doc = "Signal `adc3_dma` selected as request input"]
ADC3_DMA,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl DMAREQ_IDR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
DMAREQ_IDR::NONE => 0,
DMAREQ_IDR::DMAMUX1_REQ_GEN0 => 0x01,
DMAREQ_IDR::DMAMUX1_REQ_GEN1 => 0x02,
DMAREQ_IDR::DMAMUX1_REQ_GEN2 => 0x03,
DMAREQ_IDR::DMAMUX1_REQ_GEN3 => 0x04,
DMAREQ_IDR::DMAMUX1_REQ_GEN4 => 0x05,
DMAREQ_IDR::DMAMUX1_REQ_GEN5 => 0x06,
DMAREQ_IDR::DMAMUX1_REQ_GEN6 => 0x07,
DMAREQ_IDR::DMAMUX1_REQ_GEN7 => 0x08,
DMAREQ_IDR::ADC1_DMA => 0x09,
DMAREQ_IDR::ADC2_DMA => 0x0a,
DMAREQ_IDR::TIM1_CH1 => 0x0b,
DMAREQ_IDR::TIM1_CH2 => 0x0c,
DMAREQ_IDR::TIM1_CH3 => 0x0d,
DMAREQ_IDR::TIM1_CH4 => 0x0e,
DMAREQ_IDR::TIM1_UP => 0x0f,
DMAREQ_IDR::TIM1_TRIG => 0x10,
DMAREQ_IDR::TIM1_COM => 0x11,
DMAREQ_IDR::TIM2_CH1 => 0x12,
DMAREQ_IDR::TIM2_CH2 => 0x13,
DMAREQ_IDR::TIM2_CH3 => 0x14,
DMAREQ_IDR::TIM2_CH4 => 0x15,
DMAREQ_IDR::TIM2_UP => 0x16,
DMAREQ_IDR::TIM3_CH1 => 0x17,
DMAREQ_IDR::TIM3_CH2 => 0x18,
DMAREQ_IDR::TIM3_CH3 => 0x19,
DMAREQ_IDR::TIM3_CH4 => 0x1a,
DMAREQ_IDR::TIM3_UP => 0x1b,
DMAREQ_IDR::TIM3_TRIG => 0x1c,
DMAREQ_IDR::TIM4_CH1 => 0x1d,
DMAREQ_IDR::TIM4_CH2 => 0x1e,
DMAREQ_IDR::TIM4_CH3 => 0x1f,
DMAREQ_IDR::TIM4_UP => 0x20,
DMAREQ_IDR::I2C1_RX_DMA => 0x21,
DMAREQ_IDR::I2C1_TX_DMA => 0x22,
DMAREQ_IDR::I2C2_RX_DMA => 0x23,
DMAREQ_IDR::I2C2_TX_DMA => 0x24,
DMAREQ_IDR::SPI1_RX_DMA => 0x25,
DMAREQ_IDR::SPI1_TX_DMA => 0x26,
DMAREQ_IDR::SPI2_RX_DMA => 0x27,
DMAREQ_IDR::SPI2_TX_DMA => 0x28,
DMAREQ_IDR::USART1_RX_DMA => 0x29,
DMAREQ_IDR::USART1_TX_DMA => 0x2a,
DMAREQ_IDR::USART2_RX_DMA => 0x2b,
DMAREQ_IDR::USART2_TX_DMA => 0x2c,
DMAREQ_IDR::USART3_RX_DMA => 0x2d,
DMAREQ_IDR::USART3_TX_DMA => 0x2e,
DMAREQ_IDR::TIM8_CH1 => 0x2f,
DMAREQ_IDR::TIM8_CH2 => 0x30,
DMAREQ_IDR::TIM8_CH3 => 0x31,
DMAREQ_IDR::TIM8_CH4 => 0x32,
DMAREQ_IDR::TIM8_UP => 0x33,
DMAREQ_IDR::TIM8_TRIG => 0x34,
DMAREQ_IDR::TIM8_COM => 0x35,
DMAREQ_IDR::TIM5_CH1 => 0x37,
DMAREQ_IDR::TIM5_CH2 => 0x38,
DMAREQ_IDR::TIM5_CH3 => 0x39,
DMAREQ_IDR::TIM5_CH4 => 0x3a,
DMAREQ_IDR::TIM5_UP => 0x3b,
DMAREQ_IDR::TIM5_TRIG => 0x3c,
DMAREQ_IDR::SPI3_RX_DMA => 0x3d,
DMAREQ_IDR::SPI3_TX_DMA => 0x3e,
DMAREQ_IDR::UART4_RX_DMA => 0x3f,
DMAREQ_IDR::UART4_TX_DMA => 0x40,
DMAREQ_IDR::UART5_RX_DMA => 0x41,
DMAREQ_IDR::UART5_TX_DMA => 0x42,
DMAREQ_IDR::DAC_CH1_DMA => 0x43,
DMAREQ_IDR::DAC_CH2_DMA => 0x44,
DMAREQ_IDR::TIM6_UP => 0x45,
DMAREQ_IDR::TIM7_UP => 0x46,
DMAREQ_IDR::USART6_RX_DMA => 0x47,
DMAREQ_IDR::USART6_TX_DMA => 0x48,
DMAREQ_IDR::I2C3_RX_DMA => 0x49,
DMAREQ_IDR::I2C3_TX_DMA => 0x4a,
DMAREQ_IDR::DCMI_DMA => 0x4b,
DMAREQ_IDR::CRYP_IN_DMA => 0x4c,
DMAREQ_IDR::CRYP_OUT_DMA => 0x4d,
DMAREQ_IDR::HASH_IN_DMA => 0x4e,
DMAREQ_IDR::UART7_RX_DMA => 0x4f,
DMAREQ_IDR::UART7_TX_DMA => 0x50,
DMAREQ_IDR::UART8_RX_DMA => 0x51,
DMAREQ_IDR::UART8_TX_DMA => 0x52,
DMAREQ_IDR::SPI4_RX_DMA => 0x53,
DMAREQ_IDR::SPI4_TX_DMA => 0x54,
DMAREQ_IDR::SPI5_RX_DMA => 0x55,
DMAREQ_IDR::SPI5_TX_DMA => 0x56,
DMAREQ_IDR::SAI1A_DMA => 0x57,
DMAREQ_IDR::SAI1B_DMA => 0x58,
DMAREQ_IDR::SAI2A_DMA => 0x59,
DMAREQ_IDR::SAI2B_DMA => 0x5a,
DMAREQ_IDR::SWPMI_RX_DMA => 0x5b,
DMAREQ_IDR::SWPMI_TX_DMA => 0x5c,
DMAREQ_IDR::SPDIFRX_DAT_DMA => 0x5d,
DMAREQ_IDR::SPDIFRX_CTRL_DMA => 0x5e,
DMAREQ_IDR::HR_REQ1 => 0x5f,
DMAREQ_IDR::HR_REQ2 => 0x60,
DMAREQ_IDR::HR_REQ3 => 0x61,
DMAREQ_IDR::HR_REQ4 => 0x62,
DMAREQ_IDR::HR_REQ5 => 0x63,
DMAREQ_IDR::HR_REQ6 => 0x64,
DMAREQ_IDR::DFSDM1_DMA0 => 0x65,
DMAREQ_IDR::DFSDM1_DMA1 => 0x66,
DMAREQ_IDR::DFSDM1_DMA2 => 0x67,
DMAREQ_IDR::DFSDM1_DMA3 => 0x68,
DMAREQ_IDR::TIM15_CH1 => 0x69,
DMAREQ_IDR::TIM15_UP => 0x6a,
DMAREQ_IDR::TIM15_TRIG => 0x6b,
DMAREQ_IDR::TIM15_COM => 0x6c,
DMAREQ_IDR::TIM16_CH1 => 0x6d,
DMAREQ_IDR::TIM16_UP => 0x6e,
DMAREQ_IDR::TIM17_CH1 => 0x6f,
DMAREQ_IDR::TIM17_UP => 0x70,
DMAREQ_IDR::SAI3_A_DMA => 0x71,
DMAREQ_IDR::SAI3_B_DMA => 0x72,
DMAREQ_IDR::ADC3_DMA => 0x73,
DMAREQ_IDR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> DMAREQ_IDR {
match value {
0 => DMAREQ_IDR::NONE,
1 => DMAREQ_IDR::DMAMUX1_REQ_GEN0,
2 => DMAREQ_IDR::DMAMUX1_REQ_GEN1,
3 => DMAREQ_IDR::DMAMUX1_REQ_GEN2,
4 => DMAREQ_IDR::DMAMUX1_REQ_GEN3,
5 => DMAREQ_IDR::DMAMUX1_REQ_GEN4,
6 => DMAREQ_IDR::DMAMUX1_REQ_GEN5,
7 => DMAREQ_IDR::DMAMUX1_REQ_GEN6,
8 => DMAREQ_IDR::DMAMUX1_REQ_GEN7,
9 => DMAREQ_IDR::ADC1_DMA,
10 => DMAREQ_IDR::ADC2_DMA,
11 => DMAREQ_IDR::TIM1_CH1,
12 => DMAREQ_IDR::TIM1_CH2,
13 => DMAREQ_IDR::TIM1_CH3,
14 => DMAREQ_IDR::TIM1_CH4,
15 => DMAREQ_IDR::TIM1_UP,
16 => DMAREQ_IDR::TIM1_TRIG,
17 => DMAREQ_IDR::TIM1_COM,
18 => DMAREQ_IDR::TIM2_CH1,
19 => DMAREQ_IDR::TIM2_CH2,
20 => DMAREQ_IDR::TIM2_CH3,
21 => DMAREQ_IDR::TIM2_CH4,
22 => DMAREQ_IDR::TIM2_UP,
23 => DMAREQ_IDR::TIM3_CH1,
24 => DMAREQ_IDR::TIM3_CH2,
25 => DMAREQ_IDR::TIM3_CH3,
26 => DMAREQ_IDR::TIM3_CH4,
27 => DMAREQ_IDR::TIM3_UP,
28 => DMAREQ_IDR::TIM3_TRIG,
29 => DMAREQ_IDR::TIM4_CH1,
30 => DMAREQ_IDR::TIM4_CH2,
31 => DMAREQ_IDR::TIM4_CH3,
32 => DMAREQ_IDR::TIM4_UP,
33 => DMAREQ_IDR::I2C1_RX_DMA,
34 => DMAREQ_IDR::I2C1_TX_DMA,
35 => DMAREQ_IDR::I2C2_RX_DMA,
36 => DMAREQ_IDR::I2C2_TX_DMA,
37 => DMAREQ_IDR::SPI1_RX_DMA,
38 => DMAREQ_IDR::SPI1_TX_DMA,
39 => DMAREQ_IDR::SPI2_RX_DMA,
40 => DMAREQ_IDR::SPI2_TX_DMA,
41 => DMAREQ_IDR::USART1_RX_DMA,
42 => DMAREQ_IDR::USART1_TX_DMA,
43 => DMAREQ_IDR::USART2_RX_DMA,
44 => DMAREQ_IDR::USART2_TX_DMA,
45 => DMAREQ_IDR::USART3_RX_DMA,
46 => DMAREQ_IDR::USART3_TX_DMA,
47 => DMAREQ_IDR::TIM8_CH1,
48 => DMAREQ_IDR::TIM8_CH2,
49 => DMAREQ_IDR::TIM8_CH3,
50 => DMAREQ_IDR::TIM8_CH4,
51 => DMAREQ_IDR::TIM8_UP,
52 => DMAREQ_IDR::TIM8_TRIG,
53 => DMAREQ_IDR::TIM8_COM,
55 => DMAREQ_IDR::TIM5_CH1,
56 => DMAREQ_IDR::TIM5_CH2,
57 => DMAREQ_IDR::TIM5_CH3,
58 => DMAREQ_IDR::TIM5_CH4,
59 => DMAREQ_IDR::TIM5_UP,
60 => DMAREQ_IDR::TIM5_TRIG,
61 => DMAREQ_IDR::SPI3_RX_DMA,
62 => DMAREQ_IDR::SPI3_TX_DMA,
63 => DMAREQ_IDR::UART4_RX_DMA,
64 => DMAREQ_IDR::UART4_TX_DMA,
65 => DMAREQ_IDR::UART5_RX_DMA,
66 => DMAREQ_IDR::UART5_TX_DMA,
67 => DMAREQ_IDR::DAC_CH1_DMA,
68 => DMAREQ_IDR::DAC_CH2_DMA,
69 => DMAREQ_IDR::TIM6_UP,
70 => DMAREQ_IDR::TIM7_UP,
71 => DMAREQ_IDR::USART6_RX_DMA,
72 => DMAREQ_IDR::USART6_TX_DMA,
73 => DMAREQ_IDR::I2C3_RX_DMA,
74 => DMAREQ_IDR::I2C3_TX_DMA,
75 => DMAREQ_IDR::DCMI_DMA,
76 => DMAREQ_IDR::CRYP_IN_DMA,
77 => DMAREQ_IDR::CRYP_OUT_DMA,
78 => DMAREQ_IDR::HASH_IN_DMA,
79 => DMAREQ_IDR::UART7_RX_DMA,
80 => DMAREQ_IDR::UART7_TX_DMA,
81 => DMAREQ_IDR::UART8_RX_DMA,
82 => DMAREQ_IDR::UART8_TX_DMA,
83 => DMAREQ_IDR::SPI4_RX_DMA,
84 => DMAREQ_IDR::SPI4_TX_DMA,
85 => DMAREQ_IDR::SPI5_RX_DMA,
86 => DMAREQ_IDR::SPI5_TX_DMA,
87 => DMAREQ_IDR::SAI1A_DMA,
88 => DMAREQ_IDR::SAI1B_DMA,
89 => DMAREQ_IDR::SAI2A_DMA,
90 => DMAREQ_IDR::SAI2B_DMA,
91 => DMAREQ_IDR::SWPMI_RX_DMA,
92 => DMAREQ_IDR::SWPMI_TX_DMA,
93 => DMAREQ_IDR::SPDIFRX_DAT_DMA,
94 => DMAREQ_IDR::SPDIFRX_CTRL_DMA,
95 => DMAREQ_IDR::HR_REQ1,
96 => DMAREQ_IDR::HR_REQ2,
97 => DMAREQ_IDR::HR_REQ3,
98 => DMAREQ_IDR::HR_REQ4,
99 => DMAREQ_IDR::HR_REQ5,
100 => DMAREQ_IDR::HR_REQ6,
101 => DMAREQ_IDR::DFSDM1_DMA0,
102 => DMAREQ_IDR::DFSDM1_DMA1,
103 => DMAREQ_IDR::DFSDM1_DMA2,
104 => DMAREQ_IDR::DFSDM1_DMA3,
105 => DMAREQ_IDR::TIM15_CH1,
106 => DMAREQ_IDR::TIM15_UP,
107 => DMAREQ_IDR::TIM15_TRIG,
108 => DMAREQ_IDR::TIM15_COM,
109 => DMAREQ_IDR::TIM16_CH1,
110 => DMAREQ_IDR::TIM16_UP,
111 => DMAREQ_IDR::TIM17_CH1,
112 => DMAREQ_IDR::TIM17_UP,
113 => DMAREQ_IDR::SAI3_A_DMA,
114 => DMAREQ_IDR::SAI3_B_DMA,
115 => DMAREQ_IDR::ADC3_DMA,
i => DMAREQ_IDR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `NONE`"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == DMAREQ_IDR::NONE
}
#[doc = "Checks if the value of the field is `DMAMUX1_REQ_GEN0`"]
#[inline(always)]
pub fn is_dmamux1_req_gen0(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX1_REQ_GEN0
}
#[doc = "Checks if the value of the field is `DMAMUX1_REQ_GEN1`"]
#[inline(always)]
pub fn is_dmamux1_req_gen1(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX1_REQ_GEN1
}
#[doc = "Checks if the value of the field is `DMAMUX1_REQ_GEN2`"]
#[inline(always)]
pub fn is_dmamux1_req_gen2(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX1_REQ_GEN2
}
#[doc = "Checks if the value of the field is `DMAMUX1_REQ_GEN3`"]
#[inline(always)]
pub fn is_dmamux1_req_gen3(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX1_REQ_GEN3
}
#[doc = "Checks if the value of the field is `DMAMUX1_REQ_GEN4`"]
#[inline(always)]
pub fn is_dmamux1_req_gen4(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX1_REQ_GEN4
}
#[doc = "Checks if the value of the field is `DMAMUX1_REQ_GEN5`"]
#[inline(always)]
pub fn is_dmamux1_req_gen5(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX1_REQ_GEN5
}
#[doc = "Checks if the value of the field is `DMAMUX1_REQ_GEN6`"]
#[inline(always)]
pub fn is_dmamux1_req_gen6(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX1_REQ_GEN6
}
#[doc = "Checks if the value of the field is `DMAMUX1_REQ_GEN7`"]
#[inline(always)]
pub fn is_dmamux1_req_gen7(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX1_REQ_GEN7
}
#[doc = "Checks if the value of the field is `ADC1_DMA`"]
#[inline(always)]
pub fn is_adc1_dma(&self) -> bool {
*self == DMAREQ_IDR::ADC1_DMA
}
#[doc = "Checks if the value of the field is `ADC2_DMA`"]
#[inline(always)]
pub fn is_adc2_dma(&self) -> bool {
*self == DMAREQ_IDR::ADC2_DMA
}
#[doc = "Checks if the value of the field is `TIM1_CH1`"]
#[inline(always)]
pub fn is_tim1_ch1(&self) -> bool {
*self == DMAREQ_IDR::TIM1_CH1
}
#[doc = "Checks if the value of the field is `TIM1_CH2`"]
#[inline(always)]
pub fn is_tim1_ch2(&self) -> bool {
*self == DMAREQ_IDR::TIM1_CH2
}
#[doc = "Checks if the value of the field is `TIM1_CH3`"]
#[inline(always)]
pub fn is_tim1_ch3(&self) -> bool {
*self == DMAREQ_IDR::TIM1_CH3
}
#[doc = "Checks if the value of the field is `TIM1_CH4`"]
#[inline(always)]
pub fn is_tim1_ch4(&self) -> bool {
*self == DMAREQ_IDR::TIM1_CH4
}
#[doc = "Checks if the value of the field is `TIM1_UP`"]
#[inline(always)]
pub fn is_tim1_up(&self) -> bool {
*self == DMAREQ_IDR::TIM1_UP
}
#[doc = "Checks if the value of the field is `TIM1_TRIG`"]
#[inline(always)]
pub fn is_tim1_trig(&self) -> bool {
*self == DMAREQ_IDR::TIM1_TRIG
}
#[doc = "Checks if the value of the field is `TIM1_COM`"]
#[inline(always)]
pub fn is_tim1_com(&self) -> bool {
*self == DMAREQ_IDR::TIM1_COM
}
#[doc = "Checks if the value of the field is `TIM2_CH1`"]
#[inline(always)]
pub fn is_tim2_ch1(&self) -> bool {
*self == DMAREQ_IDR::TIM2_CH1
}
#[doc = "Checks if the value of the field is `TIM2_CH2`"]
#[inline(always)]
pub fn is_tim2_ch2(&self) -> bool {
*self == DMAREQ_IDR::TIM2_CH2
}
#[doc = "Checks if the value of the field is `TIM2_CH3`"]
#[inline(always)]
pub fn is_tim2_ch3(&self) -> bool {
*self == DMAREQ_IDR::TIM2_CH3
}
#[doc = "Checks if the value of the field is `TIM2_CH4`"]
#[inline(always)]
pub fn is_tim2_ch4(&self) -> bool {
*self == DMAREQ_IDR::TIM2_CH4
}
#[doc = "Checks if the value of the field is `TIM2_UP`"]
#[inline(always)]
pub fn is_tim2_up(&self) -> bool {
*self == DMAREQ_IDR::TIM2_UP
}
#[doc = "Checks if the value of the field is `TIM3_CH1`"]
#[inline(always)]
pub fn is_tim3_ch1(&self) -> bool {
*self == DMAREQ_IDR::TIM3_CH1
}
#[doc = "Checks if the value of the field is `TIM3_CH2`"]
#[inline(always)]
pub fn is_tim3_ch2(&self) -> bool {
*self == DMAREQ_IDR::TIM3_CH2
}
#[doc = "Checks if the value of the field is `TIM3_CH3`"]
#[inline(always)]
pub fn is_tim3_ch3(&self) -> bool {
*self == DMAREQ_IDR::TIM3_CH3
}
#[doc = "Checks if the value of the field is `TIM3_CH4`"]
#[inline(always)]
pub fn is_tim3_ch4(&self) -> bool {
*self == DMAREQ_IDR::TIM3_CH4
}
#[doc = "Checks if the value of the field is `TIM3_UP`"]
#[inline(always)]
pub fn is_tim3_up(&self) -> bool {
*self == DMAREQ_IDR::TIM3_UP
}
#[doc = "Checks if the value of the field is `TIM3_TRIG`"]
#[inline(always)]
pub fn is_tim3_trig(&self) -> bool {
*self == DMAREQ_IDR::TIM3_TRIG
}
#[doc = "Checks if the value of the field is `TIM4_CH1`"]
#[inline(always)]
pub fn is_tim4_ch1(&self) -> bool {
*self == DMAREQ_IDR::TIM4_CH1
}
#[doc = "Checks if the value of the field is `TIM4_CH2`"]
#[inline(always)]
pub fn is_tim4_ch2(&self) -> bool {
*self == DMAREQ_IDR::TIM4_CH2
}
#[doc = "Checks if the value of the field is `TIM4_CH3`"]
#[inline(always)]
pub fn is_tim4_ch3(&self) -> bool {
*self == DMAREQ_IDR::TIM4_CH3
}
#[doc = "Checks if the value of the field is `TIM4_UP`"]
#[inline(always)]
pub fn is_tim4_up(&self) -> bool {
*self == DMAREQ_IDR::TIM4_UP
}
#[doc = "Checks if the value of the field is `I2C1_RX_DMA`"]
#[inline(always)]
pub fn is_i2c1_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::I2C1_RX_DMA
}
#[doc = "Checks if the value of the field is `I2C1_TX_DMA`"]
#[inline(always)]
pub fn is_i2c1_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::I2C1_TX_DMA
}
#[doc = "Checks if the value of the field is `I2C2_RX_DMA`"]
#[inline(always)]
pub fn is_i2c2_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::I2C2_RX_DMA
}
#[doc = "Checks if the value of the field is `I2C2_TX_DMA`"]
#[inline(always)]
pub fn is_i2c2_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::I2C2_TX_DMA
}
#[doc = "Checks if the value of the field is `SPI1_RX_DMA`"]
#[inline(always)]
pub fn is_spi1_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI1_RX_DMA
}
#[doc = "Checks if the value of the field is `SPI1_TX_DMA`"]
#[inline(always)]
pub fn is_spi1_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI1_TX_DMA
}
#[doc = "Checks if the value of the field is `SPI2_RX_DMA`"]
#[inline(always)]
pub fn is_spi2_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI2_RX_DMA
}
#[doc = "Checks if the value of the field is `SPI2_TX_DMA`"]
#[inline(always)]
pub fn is_spi2_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI2_TX_DMA
}
#[doc = "Checks if the value of the field is `USART1_RX_DMA`"]
#[inline(always)]
pub fn is_usart1_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::USART1_RX_DMA
}
#[doc = "Checks if the value of the field is `USART1_TX_DMA`"]
#[inline(always)]
pub fn is_usart1_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::USART1_TX_DMA
}
#[doc = "Checks if the value of the field is `USART2_RX_DMA`"]
#[inline(always)]
pub fn is_usart2_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::USART2_RX_DMA
}
#[doc = "Checks if the value of the field is `USART2_TX_DMA`"]
#[inline(always)]
pub fn is_usart2_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::USART2_TX_DMA
}
#[doc = "Checks if the value of the field is `USART3_RX_DMA`"]
#[inline(always)]
pub fn is_usart3_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::USART3_RX_DMA
}
#[doc = "Checks if the value of the field is `USART3_TX_DMA`"]
#[inline(always)]
pub fn is_usart3_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::USART3_TX_DMA
}
#[doc = "Checks if the value of the field is `TIM8_CH1`"]
#[inline(always)]
pub fn is_tim8_ch1(&self) -> bool {
*self == DMAREQ_IDR::TIM8_CH1
}
#[doc = "Checks if the value of the field is `TIM8_CH2`"]
#[inline(always)]
pub fn is_tim8_ch2(&self) -> bool {
*self == DMAREQ_IDR::TIM8_CH2
}
#[doc = "Checks if the value of the field is `TIM8_CH3`"]
#[inline(always)]
pub fn is_tim8_ch3(&self) -> bool {
*self == DMAREQ_IDR::TIM8_CH3
}
#[doc = "Checks if the value of the field is `TIM8_CH4`"]
#[inline(always)]
pub fn is_tim8_ch4(&self) -> bool {
*self == DMAREQ_IDR::TIM8_CH4
}
#[doc = "Checks if the value of the field is `TIM8_UP`"]
#[inline(always)]
pub fn is_tim8_up(&self) -> bool {
*self == DMAREQ_IDR::TIM8_UP
}
#[doc = "Checks if the value of the field is `TIM8_TRIG`"]
#[inline(always)]
pub fn is_tim8_trig(&self) -> bool {
*self == DMAREQ_IDR::TIM8_TRIG
}
#[doc = "Checks if the value of the field is `TIM8_COM`"]
#[inline(always)]
pub fn is_tim8_com(&self) -> bool {
*self == DMAREQ_IDR::TIM8_COM
}
#[doc = "Checks if the value of the field is `TIM5_CH1`"]
#[inline(always)]
pub fn is_tim5_ch1(&self) -> bool {
*self == DMAREQ_IDR::TIM5_CH1
}
#[doc = "Checks if the value of the field is `TIM5_CH2`"]
#[inline(always)]
pub fn is_tim5_ch2(&self) -> bool {
*self == DMAREQ_IDR::TIM5_CH2
}
#[doc = "Checks if the value of the field is `TIM5_CH3`"]
#[inline(always)]
pub fn is_tim5_ch3(&self) -> bool {
*self == DMAREQ_IDR::TIM5_CH3
}
#[doc = "Checks if the value of the field is `TIM5_CH4`"]
#[inline(always)]
pub fn is_tim5_ch4(&self) -> bool {
*self == DMAREQ_IDR::TIM5_CH4
}
#[doc = "Checks if the value of the field is `TIM5_UP`"]
#[inline(always)]
pub fn is_tim5_up(&self) -> bool {
*self == DMAREQ_IDR::TIM5_UP
}
#[doc = "Checks if the value of the field is `TIM5_TRIG`"]
#[inline(always)]
pub fn is_tim5_trig(&self) -> bool {
*self == DMAREQ_IDR::TIM5_TRIG
}
#[doc = "Checks if the value of the field is `SPI3_RX_DMA`"]
#[inline(always)]
pub fn is_spi3_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI3_RX_DMA
}
#[doc = "Checks if the value of the field is `SPI3_TX_DMA`"]
#[inline(always)]
pub fn is_spi3_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI3_TX_DMA
}
#[doc = "Checks if the value of the field is `UART4_RX_DMA`"]
#[inline(always)]
pub fn is_uart4_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::UART4_RX_DMA
}
#[doc = "Checks if the value of the field is `UART4_TX_DMA`"]
#[inline(always)]
pub fn is_uart4_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::UART4_TX_DMA
}
#[doc = "Checks if the value of the field is `UART5_RX_DMA`"]
#[inline(always)]
pub fn is_uart5_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::UART5_RX_DMA
}
#[doc = "Checks if the value of the field is `UART5_TX_DMA`"]
#[inline(always)]
pub fn is_uart5_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::UART5_TX_DMA
}
#[doc = "Checks if the value of the field is `DAC_CH1_DMA`"]
#[inline(always)]
pub fn is_dac_ch1_dma(&self) -> bool {
*self == DMAREQ_IDR::DAC_CH1_DMA
}
#[doc = "Checks if the value of the field is `DAC_CH2_DMA`"]
#[inline(always)]
pub fn is_dac_ch2_dma(&self) -> bool {
*self == DMAREQ_IDR::DAC_CH2_DMA
}
#[doc = "Checks if the value of the field is `TIM6_UP`"]
#[inline(always)]
pub fn is_tim6_up(&self) -> bool {
*self == DMAREQ_IDR::TIM6_UP
}
#[doc = "Checks if the value of the field is `TIM7_UP`"]
#[inline(always)]
pub fn is_tim7_up(&self) -> bool {
*self == DMAREQ_IDR::TIM7_UP
}
#[doc = "Checks if the value of the field is `USART6_RX_DMA`"]
#[inline(always)]
pub fn is_usart6_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::USART6_RX_DMA
}
#[doc = "Checks if the value of the field is `USART6_TX_DMA`"]
#[inline(always)]
pub fn is_usart6_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::USART6_TX_DMA
}
#[doc = "Checks if the value of the field is `I2C3_RX_DMA`"]
#[inline(always)]
pub fn is_i2c3_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::I2C3_RX_DMA
}
#[doc = "Checks if the value of the field is `I2C3_TX_DMA`"]
#[inline(always)]
pub fn is_i2c3_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::I2C3_TX_DMA
}
#[doc = "Checks if the value of the field is `DCMI_DMA`"]
#[inline(always)]
pub fn is_dcmi_dma(&self) -> bool {
*self == DMAREQ_IDR::DCMI_DMA
}
#[doc = "Checks if the value of the field is `CRYP_IN_DMA`"]
#[inline(always)]
pub fn is_cryp_in_dma(&self) -> bool {
*self == DMAREQ_IDR::CRYP_IN_DMA
}
#[doc = "Checks if the value of the field is `CRYP_OUT_DMA`"]
#[inline(always)]
pub fn is_cryp_out_dma(&self) -> bool {
*self == DMAREQ_IDR::CRYP_OUT_DMA
}
#[doc = "Checks if the value of the field is `HASH_IN_DMA`"]
#[inline(always)]
pub fn is_hash_in_dma(&self) -> bool {
*self == DMAREQ_IDR::HASH_IN_DMA
}
#[doc = "Checks if the value of the field is `UART7_RX_DMA`"]
#[inline(always)]
pub fn is_uart7_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::UART7_RX_DMA
}
#[doc = "Checks if the value of the field is `UART7_TX_DMA`"]
#[inline(always)]
pub fn is_uart7_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::UART7_TX_DMA
}
#[doc = "Checks if the value of the field is `UART8_RX_DMA`"]
#[inline(always)]
pub fn is_uart8_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::UART8_RX_DMA
}
#[doc = "Checks if the value of the field is `UART8_TX_DMA`"]
#[inline(always)]
pub fn is_uart8_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::UART8_TX_DMA
}
#[doc = "Checks if the value of the field is `SPI4_RX_DMA`"]
#[inline(always)]
pub fn is_spi4_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI4_RX_DMA
}
#[doc = "Checks if the value of the field is `SPI4_TX_DMA`"]
#[inline(always)]
pub fn is_spi4_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI4_TX_DMA
}
#[doc = "Checks if the value of the field is `SPI5_RX_DMA`"]
#[inline(always)]
pub fn is_spi5_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI5_RX_DMA
}
#[doc = "Checks if the value of the field is `SPI5_TX_DMA`"]
#[inline(always)]
pub fn is_spi5_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI5_TX_DMA
}
#[doc = "Checks if the value of the field is `SAI1A_DMA`"]
#[inline(always)]
pub fn is_sai1a_dma(&self) -> bool {
*self == DMAREQ_IDR::SAI1A_DMA
}
#[doc = "Checks if the value of the field is `SAI1B_DMA`"]
#[inline(always)]
pub fn is_sai1b_dma(&self) -> bool {
*self == DMAREQ_IDR::SAI1B_DMA
}
#[doc = "Checks if the value of the field is `SAI2A_DMA`"]
#[inline(always)]
pub fn is_sai2a_dma(&self) -> bool {
*self == DMAREQ_IDR::SAI2A_DMA
}
#[doc = "Checks if the value of the field is `SAI2B_DMA`"]
#[inline(always)]
pub fn is_sai2b_dma(&self) -> bool {
*self == DMAREQ_IDR::SAI2B_DMA
}
#[doc = "Checks if the value of the field is `SWPMI_RX_DMA`"]
#[inline(always)]
pub fn is_swpmi_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::SWPMI_RX_DMA
}
#[doc = "Checks if the value of the field is `SWPMI_TX_DMA`"]
#[inline(always)]
pub fn is_swpmi_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::SWPMI_TX_DMA
}
#[doc = "Checks if the value of the field is `SPDIFRX_DAT_DMA`"]
#[inline(always)]
pub fn is_spdifrx_dat_dma(&self) -> bool {
*self == DMAREQ_IDR::SPDIFRX_DAT_DMA
}
#[doc = "Checks if the value of the field is `SPDIFRX_CTRL_DMA`"]
#[inline(always)]
pub fn is_spdifrx_ctrl_dma(&self) -> bool {
*self == DMAREQ_IDR::SPDIFRX_CTRL_DMA
}
#[doc = "Checks if the value of the field is `HR_REQ1`"]
#[inline(always)]
pub fn is_hr_req1(&self) -> bool {
*self == DMAREQ_IDR::HR_REQ1
}
#[doc = "Checks if the value of the field is `HR_REQ2`"]
#[inline(always)]
pub fn is_hr_req2(&self) -> bool {
*self == DMAREQ_IDR::HR_REQ2
}
#[doc = "Checks if the value of the field is `HR_REQ3`"]
#[inline(always)]
pub fn is_hr_req3(&self) -> bool {
*self == DMAREQ_IDR::HR_REQ3
}
#[doc = "Checks if the value of the field is `HR_REQ4`"]
#[inline(always)]
pub fn is_hr_req4(&self) -> bool {
*self == DMAREQ_IDR::HR_REQ4
}
#[doc = "Checks if the value of the field is `HR_REQ5`"]
#[inline(always)]
pub fn is_hr_req5(&self) -> bool {
*self == DMAREQ_IDR::HR_REQ5
}
#[doc = "Checks if the value of the field is `HR_REQ6`"]
#[inline(always)]
pub fn is_hr_req6(&self) -> bool {
*self == DMAREQ_IDR::HR_REQ6
}
#[doc = "Checks if the value of the field is `DFSDM1_DMA0`"]
#[inline(always)]
pub fn is_dfsdm1_dma0(&self) -> bool {
*self == DMAREQ_IDR::DFSDM1_DMA0
}
#[doc = "Checks if the value of the field is `DFSDM1_DMA1`"]
#[inline(always)]
pub fn is_dfsdm1_dma1(&self) -> bool {
*self == DMAREQ_IDR::DFSDM1_DMA1
}
#[doc = "Checks if the value of the field is `DFSDM1_DMA2`"]
#[inline(always)]
pub fn is_dfsdm1_dma2(&self) -> bool {
*self == DMAREQ_IDR::DFSDM1_DMA2
}
#[doc = "Checks if the value of the field is `DFSDM1_DMA3`"]
#[inline(always)]
pub fn is_dfsdm1_dma3(&self) -> bool {
*self == DMAREQ_IDR::DFSDM1_DMA3
}
#[doc = "Checks if the value of the field is `TIM15_CH1`"]
#[inline(always)]
pub fn is_tim15_ch1(&self) -> bool {
*self == DMAREQ_IDR::TIM15_CH1
}
#[doc = "Checks if the value of the field is `TIM15_UP`"]
#[inline(always)]
pub fn is_tim15_up(&self) -> bool {
*self == DMAREQ_IDR::TIM15_UP
}
#[doc = "Checks if the value of the field is `TIM15_TRIG`"]
#[inline(always)]
pub fn is_tim15_trig(&self) -> bool {
*self == DMAREQ_IDR::TIM15_TRIG
}
#[doc = "Checks if the value of the field is `TIM15_COM`"]
#[inline(always)]
pub fn is_tim15_com(&self) -> bool {
*self == DMAREQ_IDR::TIM15_COM
}
#[doc = "Checks if the value of the field is `TIM16_CH1`"]
#[inline(always)]
pub fn is_tim16_ch1(&self) -> bool {
*self == DMAREQ_IDR::TIM16_CH1
}
#[doc = "Checks if the value of the field is `TIM16_UP`"]
#[inline(always)]
pub fn is_tim16_up(&self) -> bool {
*self == DMAREQ_IDR::TIM16_UP
}
#[doc = "Checks if the value of the field is `TIM17_CH1`"]
#[inline(always)]
pub fn is_tim17_ch1(&self) -> bool {
*self == DMAREQ_IDR::TIM17_CH1
}
#[doc = "Checks if the value of the field is `TIM17_UP`"]
#[inline(always)]
pub fn is_tim17_up(&self) -> bool {
*self == DMAREQ_IDR::TIM17_UP
}
#[doc = "Checks if the value of the field is `SAI3_A_DMA`"]
#[inline(always)]
pub fn is_sai3_a_dma(&self) -> bool {
*self == DMAREQ_IDR::SAI3_A_DMA
}
#[doc = "Checks if the value of the field is `SAI3_B_DMA`"]
#[inline(always)]
pub fn is_sai3_b_dma(&self) -> bool {
*self == DMAREQ_IDR::SAI3_B_DMA
}
#[doc = "Checks if the value of the field is `ADC3_DMA`"]
#[inline(always)]
pub fn is_adc3_dma(&self) -> bool {
*self == DMAREQ_IDR::ADC3_DMA
}
}
#[doc = "Values that can be written to the field `DMAREQ_ID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAREQ_IDW {
#[doc = "No signal selected as request input"]
NONE,
#[doc = "Signal `dmamux1_req_gen0` selected as request input"]
DMAMUX1_REQ_GEN0,
#[doc = "Signal `dmamux1_req_gen1` selected as request input"]
DMAMUX1_REQ_GEN1,
#[doc = "Signal `dmamux1_req_gen2` selected as request input"]
DMAMUX1_REQ_GEN2,
#[doc = "Signal `dmamux1_req_gen3` selected as request input"]
DMAMUX1_REQ_GEN3,
#[doc = "Signal `dmamux1_req_gen4` selected as request input"]
DMAMUX1_REQ_GEN4,
#[doc = "Signal `dmamux1_req_gen5` selected as request input"]
DMAMUX1_REQ_GEN5,
#[doc = "Signal `dmamux1_req_gen6` selected as request input"]
DMAMUX1_REQ_GEN6,
#[doc = "Signal `dmamux1_req_gen7` selected as request input"]
DMAMUX1_REQ_GEN7,
#[doc = "Signal `adc1_dma` selected as request input"]
ADC1_DMA,
#[doc = "Signal `adc2_dma` selected as request input"]
ADC2_DMA,
#[doc = "Signal `tim1_ch1` selected as request input"]
TIM1_CH1,
#[doc = "Signal `tim1_ch2` selected as request input"]
TIM1_CH2,
#[doc = "Signal `tim1_ch3` selected as request input"]
TIM1_CH3,
#[doc = "Signal `tim1_ch4` selected as request input"]
TIM1_CH4,
#[doc = "Signal `tim1_up` selected as request input"]
TIM1_UP,
#[doc = "Signal `tim1_trig` selected as request input"]
TIM1_TRIG,
#[doc = "Signal `tim1_com` selected as request input"]
TIM1_COM,
#[doc = "Signal `tim2_ch1` selected as request input"]
TIM2_CH1,
#[doc = "Signal `tim2_ch2` selected as request input"]
TIM2_CH2,
#[doc = "Signal `tim2_ch3` selected as request input"]
TIM2_CH3,
#[doc = "Signal `tim2_ch4` selected as request input"]
TIM2_CH4,
#[doc = "Signal `tim2_up` selected as request input"]
TIM2_UP,
#[doc = "Signal `tim3_ch1` selected as request input"]
TIM3_CH1,
#[doc = "Signal `tim3_ch2` selected as request input"]
TIM3_CH2,
#[doc = "Signal `tim3_ch3` selected as request input"]
TIM3_CH3,
#[doc = "Signal `tim3_ch4` selected as request input"]
TIM3_CH4,
#[doc = "Signal `tim3_up` selected as request input"]
TIM3_UP,
#[doc = "Signal `tim3_trig` selected as request input"]
TIM3_TRIG,
#[doc = "Signal `tim4_ch1` selected as request input"]
TIM4_CH1,
#[doc = "Signal `tim4_ch2` selected as request input"]
TIM4_CH2,
#[doc = "Signal `tim4_ch3` selected as request input"]
TIM4_CH3,
#[doc = "Signal `tim4_up` selected as request input"]
TIM4_UP,
#[doc = "Signal `i2c1_rx_dma` selected as request input"]
I2C1_RX_DMA,
#[doc = "Signal `i2c1_tx_dma` selected as request input"]
I2C1_TX_DMA,
#[doc = "Signal `i2c2_rx_dma` selected as request input"]
I2C2_RX_DMA,
#[doc = "Signal `i2c2_tx_dma` selected as request input"]
I2C2_TX_DMA,
#[doc = "Signal `spi1_rx_dma` selected as request input"]
SPI1_RX_DMA,
#[doc = "Signal `spi1_tx_dma` selected as request input"]
SPI1_TX_DMA,
#[doc = "Signal `spi2_rx_dma` selected as request input"]
SPI2_RX_DMA,
#[doc = "Signal `spi2_tx_dma` selected as request input"]
SPI2_TX_DMA,
#[doc = "Signal `usart1_rx_dma` selected as request input"]
USART1_RX_DMA,
#[doc = "Signal `usart1_tx_dma` selected as request input"]
USART1_TX_DMA,
#[doc = "Signal `usart2_rx_dma` selected as request input"]
USART2_RX_DMA,
#[doc = "Signal `usart2_tx_dma` selected as request input"]
USART2_TX_DMA,
#[doc = "Signal `usart3_rx_dma` selected as request input"]
USART3_RX_DMA,
#[doc = "Signal `usart3_tx_dma` selected as request input"]
USART3_TX_DMA,
#[doc = "Signal `tim8_ch1` selected as request input"]
TIM8_CH1,
#[doc = "Signal `tim8_ch2` selected as request input"]
TIM8_CH2,
#[doc = "Signal `tim8_ch3` selected as request input"]
TIM8_CH3,
#[doc = "Signal `tim8_ch4` selected as request input"]
TIM8_CH4,
#[doc = "Signal `tim8_up` selected as request input"]
TIM8_UP,
#[doc = "Signal `tim8_trig` selected as request input"]
TIM8_TRIG,
#[doc = "Signal `tim8_com` selected as request input"]
TIM8_COM,
#[doc = "Signal `tim5_ch1` selected as request input"]
TIM5_CH1,
#[doc = "Signal `tim5_ch2` selected as request input"]
TIM5_CH2,
#[doc = "Signal `tim5_ch3` selected as request input"]
TIM5_CH3,
#[doc = "Signal `tim5_ch4` selected as request input"]
TIM5_CH4,
#[doc = "Signal `tim5_up` selected as request input"]
TIM5_UP,
#[doc = "Signal `tim5_trig` selected as request input"]
TIM5_TRIG,
#[doc = "Signal `spi3_rx_dma` selected as request input"]
SPI3_RX_DMA,
#[doc = "Signal `spi3_tx_dma` selected as request input"]
SPI3_TX_DMA,
#[doc = "Signal `uart4_rx_dma` selected as request input"]
UART4_RX_DMA,
#[doc = "Signal `uart4_tx_dma` selected as request input"]
UART4_TX_DMA,
#[doc = "Signal `uart5_rx_dma` selected as request input"]
UART5_RX_DMA,
#[doc = "Signal `uart5_tx_dma` selected as request input"]
UART5_TX_DMA,
#[doc = "Signal `dac_ch1_dma` selected as request input"]
DAC_CH1_DMA,
#[doc = "Signal `dac_ch2_dma` selected as request input"]
DAC_CH2_DMA,
#[doc = "Signal `tim6_up` selected as request input"]
TIM6_UP,
#[doc = "Signal `tim7_up` selected as request input"]
TIM7_UP,
#[doc = "Signal `usart6_rx_dma` selected as request input"]
USART6_RX_DMA,
#[doc = "Signal `usart6_tx_dma` selected as request input"]
USART6_TX_DMA,
#[doc = "Signal `i2c3_rx_dma` selected as request input"]
I2C3_RX_DMA,
#[doc = "Signal `i2c3_tx_dma` selected as request input"]
I2C3_TX_DMA,
#[doc = "Signal `dcmi_dma` selected as request input"]
DCMI_DMA,
#[doc = "Signal `cryp_in_dma` selected as request input"]
CRYP_IN_DMA,
#[doc = "Signal `cryp_out_dma` selected as request input"]
CRYP_OUT_DMA,
#[doc = "Signal `hash_in_dma` selected as request input"]
HASH_IN_DMA,
#[doc = "Signal `uart7_rx_dma` selected as request input"]
UART7_RX_DMA,
#[doc = "Signal `uart7_tx_dma` selected as request input"]
UART7_TX_DMA,
#[doc = "Signal `uart8_rx_dma` selected as request input"]
UART8_RX_DMA,
#[doc = "Signal `uart8_tx_dma` selected as request input"]
UART8_TX_DMA,
#[doc = "Signal `spi4_rx_dma` selected as request input"]
SPI4_RX_DMA,
#[doc = "Signal `spi4_tx_dma` selected as request input"]
SPI4_TX_DMA,
#[doc = "Signal `spi5_rx_dma` selected as request input"]
SPI5_RX_DMA,
#[doc = "Signal `spi5_tx_dma` selected as request input"]
SPI5_TX_DMA,
#[doc = "Signal `sai1a_dma` selected as request input"]
SAI1A_DMA,
#[doc = "Signal `sai1b_dma` selected as request input"]
SAI1B_DMA,
#[doc = "Signal `sai2a_dma` selected as request input"]
SAI2A_DMA,
#[doc = "Signal `sai2b_dma` selected as request input"]
SAI2B_DMA,
#[doc = "Signal `swpmi_rx_dma` selected as request input"]
SWPMI_RX_DMA,
#[doc = "Signal `swpmi_tx_dma` selected as request input"]
SWPMI_TX_DMA,
#[doc = "Signal `spdifrx_dat_dma` selected as request input"]
SPDIFRX_DAT_DMA,
#[doc = "Signal `spdifrx_ctrl_dma` selected as request input"]
SPDIFRX_CTRL_DMA,
#[doc = "Signal `hr_req(1)` selected as request input"]
HR_REQ1,
#[doc = "Signal `hr_req(2)` selected as request input"]
HR_REQ2,
#[doc = "Signal `hr_req(3)` selected as request input"]
HR_REQ3,
#[doc = "Signal `hr_req(4)` selected as request input"]
HR_REQ4,
#[doc = "Signal `hr_req(5)` selected as request input"]
HR_REQ5,
#[doc = "Signal `hr_req(6)` selected as request input"]
HR_REQ6,
#[doc = "Signal `dfsdm1_dma0` selected as request input"]
DFSDM1_DMA0,
#[doc = "Signal `dfsdm1_dma1` selected as request input"]
DFSDM1_DMA1,
#[doc = "Signal `dfsdm1_dma2` selected as request input"]
DFSDM1_DMA2,
#[doc = "Signal `dfsdm1_dma3` selected as request input"]
DFSDM1_DMA3,
#[doc = "Signal `tim15_ch1` selected as request input"]
TIM15_CH1,
#[doc = "Signal `tim15_up` selected as request input"]
TIM15_UP,
#[doc = "Signal `tim15_trig` selected as request input"]
TIM15_TRIG,
#[doc = "Signal `tim15_com` selected as request input"]
TIM15_COM,
#[doc = "Signal `tim16_ch1` selected as request input"]
TIM16_CH1,
#[doc = "Signal `tim16_up` selected as request input"]
TIM16_UP,
#[doc = "Signal `tim17_ch1` selected as request input"]
TIM17_CH1,
#[doc = "Signal `tim17_up` selected as request input"]
TIM17_UP,
#[doc = "Signal `sai3_a_dma` selected as request input"]
SAI3_A_DMA,
#[doc = "Signal `sai3_b_dma` selected as request input"]
SAI3_B_DMA,
#[doc = "Signal `adc3_dma` selected as request input"]
ADC3_DMA,
}
impl DMAREQ_IDW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
DMAREQ_IDW::NONE => 0,
DMAREQ_IDW::DMAMUX1_REQ_GEN0 => 1,
DMAREQ_IDW::DMAMUX1_REQ_GEN1 => 2,
DMAREQ_IDW::DMAMUX1_REQ_GEN2 => 3,
DMAREQ_IDW::DMAMUX1_REQ_GEN3 => 4,
DMAREQ_IDW::DMAMUX1_REQ_GEN4 => 5,
DMAREQ_IDW::DMAMUX1_REQ_GEN5 => 6,
DMAREQ_IDW::DMAMUX1_REQ_GEN6 => 7,
DMAREQ_IDW::DMAMUX1_REQ_GEN7 => 8,
DMAREQ_IDW::ADC1_DMA => 9,
DMAREQ_IDW::ADC2_DMA => 10,
DMAREQ_IDW::TIM1_CH1 => 11,
DMAREQ_IDW::TIM1_CH2 => 12,
DMAREQ_IDW::TIM1_CH3 => 13,
DMAREQ_IDW::TIM1_CH4 => 14,
DMAREQ_IDW::TIM1_UP => 15,
DMAREQ_IDW::TIM1_TRIG => 16,
DMAREQ_IDW::TIM1_COM => 17,
DMAREQ_IDW::TIM2_CH1 => 18,
DMAREQ_IDW::TIM2_CH2 => 19,
DMAREQ_IDW::TIM2_CH3 => 20,
DMAREQ_IDW::TIM2_CH4 => 21,
DMAREQ_IDW::TIM2_UP => 22,
DMAREQ_IDW::TIM3_CH1 => 23,
DMAREQ_IDW::TIM3_CH2 => 24,
DMAREQ_IDW::TIM3_CH3 => 25,
DMAREQ_IDW::TIM3_CH4 => 26,
DMAREQ_IDW::TIM3_UP => 27,
DMAREQ_IDW::TIM3_TRIG => 28,
DMAREQ_IDW::TIM4_CH1 => 29,
DMAREQ_IDW::TIM4_CH2 => 30,
DMAREQ_IDW::TIM4_CH3 => 31,
DMAREQ_IDW::TIM4_UP => 32,
DMAREQ_IDW::I2C1_RX_DMA => 33,
DMAREQ_IDW::I2C1_TX_DMA => 34,
DMAREQ_IDW::I2C2_RX_DMA => 35,
DMAREQ_IDW::I2C2_TX_DMA => 36,
DMAREQ_IDW::SPI1_RX_DMA => 37,
DMAREQ_IDW::SPI1_TX_DMA => 38,
DMAREQ_IDW::SPI2_RX_DMA => 39,
DMAREQ_IDW::SPI2_TX_DMA => 40,
DMAREQ_IDW::USART1_RX_DMA => 41,
DMAREQ_IDW::USART1_TX_DMA => 42,
DMAREQ_IDW::USART2_RX_DMA => 43,
DMAREQ_IDW::USART2_TX_DMA => 44,
DMAREQ_IDW::USART3_RX_DMA => 45,
DMAREQ_IDW::USART3_TX_DMA => 46,
DMAREQ_IDW::TIM8_CH1 => 47,
DMAREQ_IDW::TIM8_CH2 => 48,
DMAREQ_IDW::TIM8_CH3 => 49,
DMAREQ_IDW::TIM8_CH4 => 50,
DMAREQ_IDW::TIM8_UP => 51,
DMAREQ_IDW::TIM8_TRIG => 52,
DMAREQ_IDW::TIM8_COM => 53,
DMAREQ_IDW::TIM5_CH1 => 55,
DMAREQ_IDW::TIM5_CH2 => 56,
DMAREQ_IDW::TIM5_CH3 => 57,
DMAREQ_IDW::TIM5_CH4 => 58,
DMAREQ_IDW::TIM5_UP => 59,
DMAREQ_IDW::TIM5_TRIG => 60,
DMAREQ_IDW::SPI3_RX_DMA => 61,
DMAREQ_IDW::SPI3_TX_DMA => 62,
DMAREQ_IDW::UART4_RX_DMA => 63,
DMAREQ_IDW::UART4_TX_DMA => 64,
DMAREQ_IDW::UART5_RX_DMA => 65,
DMAREQ_IDW::UART5_TX_DMA => 66,
DMAREQ_IDW::DAC_CH1_DMA => 67,
DMAREQ_IDW::DAC_CH2_DMA => 68,
DMAREQ_IDW::TIM6_UP => 69,
DMAREQ_IDW::TIM7_UP => 70,
DMAREQ_IDW::USART6_RX_DMA => 71,
DMAREQ_IDW::USART6_TX_DMA => 72,
DMAREQ_IDW::I2C3_RX_DMA => 73,
DMAREQ_IDW::I2C3_TX_DMA => 74,
DMAREQ_IDW::DCMI_DMA => 75,
DMAREQ_IDW::CRYP_IN_DMA => 76,
DMAREQ_IDW::CRYP_OUT_DMA => 77,
DMAREQ_IDW::HASH_IN_DMA => 78,
DMAREQ_IDW::UART7_RX_DMA => 79,
DMAREQ_IDW::UART7_TX_DMA => 80,
DMAREQ_IDW::UART8_RX_DMA => 81,
DMAREQ_IDW::UART8_TX_DMA => 82,
DMAREQ_IDW::SPI4_RX_DMA => 83,
DMAREQ_IDW::SPI4_TX_DMA => 84,
DMAREQ_IDW::SPI5_RX_DMA => 85,
DMAREQ_IDW::SPI5_TX_DMA => 86,
DMAREQ_IDW::SAI1A_DMA => 87,
DMAREQ_IDW::SAI1B_DMA => 88,
DMAREQ_IDW::SAI2A_DMA => 89,
DMAREQ_IDW::SAI2B_DMA => 90,
DMAREQ_IDW::SWPMI_RX_DMA => 91,
DMAREQ_IDW::SWPMI_TX_DMA => 92,
DMAREQ_IDW::SPDIFRX_DAT_DMA => 93,
DMAREQ_IDW::SPDIFRX_CTRL_DMA => 94,
DMAREQ_IDW::HR_REQ1 => 95,
DMAREQ_IDW::HR_REQ2 => 96,
DMAREQ_IDW::HR_REQ3 => 97,
DMAREQ_IDW::HR_REQ4 => 98,
DMAREQ_IDW::HR_REQ5 => 99,
DMAREQ_IDW::HR_REQ6 => 100,
DMAREQ_IDW::DFSDM1_DMA0 => 101,
DMAREQ_IDW::DFSDM1_DMA1 => 102,
DMAREQ_IDW::DFSDM1_DMA2 => 103,
DMAREQ_IDW::DFSDM1_DMA3 => 104,
DMAREQ_IDW::TIM15_CH1 => 105,
DMAREQ_IDW::TIM15_UP => 106,
DMAREQ_IDW::TIM15_TRIG => 107,
DMAREQ_IDW::TIM15_COM => 108,
DMAREQ_IDW::TIM16_CH1 => 109,
DMAREQ_IDW::TIM16_UP => 110,
DMAREQ_IDW::TIM17_CH1 => 111,
DMAREQ_IDW::TIM17_UP => 112,
DMAREQ_IDW::SAI3_A_DMA => 113,
DMAREQ_IDW::SAI3_B_DMA => 114,
DMAREQ_IDW::ADC3_DMA => 115,
}
}
}
#[doc = r"Proxy"]
pub struct _DMAREQ_IDW<'a> {
w: &'a mut W,
}
impl<'a> _DMAREQ_IDW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DMAREQ_IDW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "No signal selected as request input"]
#[inline(always)]
pub fn none(self) -> &'a mut W {
self.variant(DMAREQ_IDW::NONE)
}
#[doc = "Signal `dmamux1_req_gen0` selected as request input"]
#[inline(always)]
pub fn dmamux1_req_gen0(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX1_REQ_GEN0)
}
#[doc = "Signal `dmamux1_req_gen1` selected as request input"]
#[inline(always)]
pub fn dmamux1_req_gen1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX1_REQ_GEN1)
}
#[doc = "Signal `dmamux1_req_gen2` selected as request input"]
#[inline(always)]
pub fn dmamux1_req_gen2(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX1_REQ_GEN2)
}
#[doc = "Signal `dmamux1_req_gen3` selected as request input"]
#[inline(always)]
pub fn dmamux1_req_gen3(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX1_REQ_GEN3)
}
#[doc = "Signal `dmamux1_req_gen4` selected as request input"]
#[inline(always)]
pub fn dmamux1_req_gen4(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX1_REQ_GEN4)
}
#[doc = "Signal `dmamux1_req_gen5` selected as request input"]
#[inline(always)]
pub fn dmamux1_req_gen5(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX1_REQ_GEN5)
}
#[doc = "Signal `dmamux1_req_gen6` selected as request input"]
#[inline(always)]
pub fn dmamux1_req_gen6(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX1_REQ_GEN6)
}
#[doc = "Signal `dmamux1_req_gen7` selected as request input"]
#[inline(always)]
pub fn dmamux1_req_gen7(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX1_REQ_GEN7)
}
#[doc = "Signal `adc1_dma` selected as request input"]
#[inline(always)]
pub fn adc1_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::ADC1_DMA)
}
#[doc = "Signal `adc2_dma` selected as request input"]
#[inline(always)]
pub fn adc2_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::ADC2_DMA)
}
#[doc = "Signal `tim1_ch1` selected as request input"]
#[inline(always)]
pub fn tim1_ch1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM1_CH1)
}
#[doc = "Signal `tim1_ch2` selected as request input"]
#[inline(always)]
pub fn tim1_ch2(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM1_CH2)
}
#[doc = "Signal `tim1_ch3` selected as request input"]
#[inline(always)]
pub fn tim1_ch3(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM1_CH3)
}
#[doc = "Signal `tim1_ch4` selected as request input"]
#[inline(always)]
pub fn tim1_ch4(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM1_CH4)
}
#[doc = "Signal `tim1_up` selected as request input"]
#[inline(always)]
pub fn tim1_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM1_UP)
}
#[doc = "Signal `tim1_trig` selected as request input"]
#[inline(always)]
pub fn tim1_trig(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM1_TRIG)
}
#[doc = "Signal `tim1_com` selected as request input"]
#[inline(always)]
pub fn tim1_com(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM1_COM)
}
#[doc = "Signal `tim2_ch1` selected as request input"]
#[inline(always)]
pub fn tim2_ch1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM2_CH1)
}
#[doc = "Signal `tim2_ch2` selected as request input"]
#[inline(always)]
pub fn tim2_ch2(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM2_CH2)
}
#[doc = "Signal `tim2_ch3` selected as request input"]
#[inline(always)]
pub fn tim2_ch3(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM2_CH3)
}
#[doc = "Signal `tim2_ch4` selected as request input"]
#[inline(always)]
pub fn tim2_ch4(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM2_CH4)
}
#[doc = "Signal `tim2_up` selected as request input"]
#[inline(always)]
pub fn tim2_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM2_UP)
}
#[doc = "Signal `tim3_ch1` selected as request input"]
#[inline(always)]
pub fn tim3_ch1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM3_CH1)
}
#[doc = "Signal `tim3_ch2` selected as request input"]
#[inline(always)]
pub fn tim3_ch2(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM3_CH2)
}
#[doc = "Signal `tim3_ch3` selected as request input"]
#[inline(always)]
pub fn tim3_ch3(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM3_CH3)
}
#[doc = "Signal `tim3_ch4` selected as request input"]
#[inline(always)]
pub fn tim3_ch4(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM3_CH4)
}
#[doc = "Signal `tim3_up` selected as request input"]
#[inline(always)]
pub fn tim3_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM3_UP)
}
#[doc = "Signal `tim3_trig` selected as request input"]
#[inline(always)]
pub fn tim3_trig(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM3_TRIG)
}
#[doc = "Signal `tim4_ch1` selected as request input"]
#[inline(always)]
pub fn tim4_ch1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM4_CH1)
}
#[doc = "Signal `tim4_ch2` selected as request input"]
#[inline(always)]
pub fn tim4_ch2(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM4_CH2)
}
#[doc = "Signal `tim4_ch3` selected as request input"]
#[inline(always)]
pub fn tim4_ch3(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM4_CH3)
}
#[doc = "Signal `tim4_up` selected as request input"]
#[inline(always)]
pub fn tim4_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM4_UP)
}
#[doc = "Signal `i2c1_rx_dma` selected as request input"]
#[inline(always)]
pub fn i2c1_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::I2C1_RX_DMA)
}
#[doc = "Signal `i2c1_tx_dma` selected as request input"]
#[inline(always)]
pub fn i2c1_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::I2C1_TX_DMA)
}
#[doc = "Signal `i2c2_rx_dma` selected as request input"]
#[inline(always)]
pub fn i2c2_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::I2C2_RX_DMA)
}
#[doc = "Signal `i2c2_tx_dma` selected as request input"]
#[inline(always)]
pub fn i2c2_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::I2C2_TX_DMA)
}
#[doc = "Signal `spi1_rx_dma` selected as request input"]
#[inline(always)]
pub fn spi1_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI1_RX_DMA)
}
#[doc = "Signal `spi1_tx_dma` selected as request input"]
#[inline(always)]
pub fn spi1_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI1_TX_DMA)
}
#[doc = "Signal `spi2_rx_dma` selected as request input"]
#[inline(always)]
pub fn spi2_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI2_RX_DMA)
}
#[doc = "Signal `spi2_tx_dma` selected as request input"]
#[inline(always)]
pub fn spi2_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI2_TX_DMA)
}
#[doc = "Signal `usart1_rx_dma` selected as request input"]
#[inline(always)]
pub fn usart1_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::USART1_RX_DMA)
}
#[doc = "Signal `usart1_tx_dma` selected as request input"]
#[inline(always)]
pub fn usart1_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::USART1_TX_DMA)
}
#[doc = "Signal `usart2_rx_dma` selected as request input"]
#[inline(always)]
pub fn usart2_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::USART2_RX_DMA)
}
#[doc = "Signal `usart2_tx_dma` selected as request input"]
#[inline(always)]
pub fn usart2_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::USART2_TX_DMA)
}
#[doc = "Signal `usart3_rx_dma` selected as request input"]
#[inline(always)]
pub fn usart3_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::USART3_RX_DMA)
}
#[doc = "Signal `usart3_tx_dma` selected as request input"]
#[inline(always)]
pub fn usart3_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::USART3_TX_DMA)
}
#[doc = "Signal `tim8_ch1` selected as request input"]
#[inline(always)]
pub fn tim8_ch1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM8_CH1)
}
#[doc = "Signal `tim8_ch2` selected as request input"]
#[inline(always)]
pub fn tim8_ch2(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM8_CH2)
}
#[doc = "Signal `tim8_ch3` selected as request input"]
#[inline(always)]
pub fn tim8_ch3(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM8_CH3)
}
#[doc = "Signal `tim8_ch4` selected as request input"]
#[inline(always)]
pub fn tim8_ch4(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM8_CH4)
}
#[doc = "Signal `tim8_up` selected as request input"]
#[inline(always)]
pub fn tim8_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM8_UP)
}
#[doc = "Signal `tim8_trig` selected as request input"]
#[inline(always)]
pub fn tim8_trig(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM8_TRIG)
}
#[doc = "Signal `tim8_com` selected as request input"]
#[inline(always)]
pub fn tim8_com(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM8_COM)
}
#[doc = "Signal `tim5_ch1` selected as request input"]
#[inline(always)]
pub fn tim5_ch1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM5_CH1)
}
#[doc = "Signal `tim5_ch2` selected as request input"]
#[inline(always)]
pub fn tim5_ch2(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM5_CH2)
}
#[doc = "Signal `tim5_ch3` selected as request input"]
#[inline(always)]
pub fn tim5_ch3(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM5_CH3)
}
#[doc = "Signal `tim5_ch4` selected as request input"]
#[inline(always)]
pub fn tim5_ch4(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM5_CH4)
}
#[doc = "Signal `tim5_up` selected as request input"]
#[inline(always)]
pub fn tim5_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM5_UP)
}
#[doc = "Signal `tim5_trig` selected as request input"]
#[inline(always)]
pub fn tim5_trig(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM5_TRIG)
}
#[doc = "Signal `spi3_rx_dma` selected as request input"]
#[inline(always)]
pub fn spi3_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI3_RX_DMA)
}
#[doc = "Signal `spi3_tx_dma` selected as request input"]
#[inline(always)]
pub fn spi3_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI3_TX_DMA)
}
#[doc = "Signal `uart4_rx_dma` selected as request input"]
#[inline(always)]
pub fn uart4_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::UART4_RX_DMA)
}
#[doc = "Signal `uart4_tx_dma` selected as request input"]
#[inline(always)]
pub fn uart4_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::UART4_TX_DMA)
}
#[doc = "Signal `uart5_rx_dma` selected as request input"]
#[inline(always)]
pub fn uart5_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::UART5_RX_DMA)
}
#[doc = "Signal `uart5_tx_dma` selected as request input"]
#[inline(always)]
pub fn uart5_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::UART5_TX_DMA)
}
#[doc = "Signal `dac_ch1_dma` selected as request input"]
#[inline(always)]
pub fn dac_ch1_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DAC_CH1_DMA)
}
#[doc = "Signal `dac_ch2_dma` selected as request input"]
#[inline(always)]
pub fn dac_ch2_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DAC_CH2_DMA)
}
#[doc = "Signal `tim6_up` selected as request input"]
#[inline(always)]
pub fn tim6_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM6_UP)
}
#[doc = "Signal `tim7_up` selected as request input"]
#[inline(always)]
pub fn tim7_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM7_UP)
}
#[doc = "Signal `usart6_rx_dma` selected as request input"]
#[inline(always)]
pub fn usart6_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::USART6_RX_DMA)
}
#[doc = "Signal `usart6_tx_dma` selected as request input"]
#[inline(always)]
pub fn usart6_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::USART6_TX_DMA)
}
#[doc = "Signal `i2c3_rx_dma` selected as request input"]
#[inline(always)]
pub fn i2c3_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::I2C3_RX_DMA)
}
#[doc = "Signal `i2c3_tx_dma` selected as request input"]
#[inline(always)]
pub fn i2c3_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::I2C3_TX_DMA)
}
#[doc = "Signal `dcmi_dma` selected as request input"]
#[inline(always)]
pub fn dcmi_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DCMI_DMA)
}
#[doc = "Signal `cryp_in_dma` selected as request input"]
#[inline(always)]
pub fn cryp_in_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::CRYP_IN_DMA)
}
#[doc = "Signal `cryp_out_dma` selected as request input"]
#[inline(always)]
pub fn cryp_out_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::CRYP_OUT_DMA)
}
#[doc = "Signal `hash_in_dma` selected as request input"]
#[inline(always)]
pub fn hash_in_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::HASH_IN_DMA)
}
#[doc = "Signal `uart7_rx_dma` selected as request input"]
#[inline(always)]
pub fn uart7_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::UART7_RX_DMA)
}
#[doc = "Signal `uart7_tx_dma` selected as request input"]
#[inline(always)]
pub fn uart7_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::UART7_TX_DMA)
}
#[doc = "Signal `uart8_rx_dma` selected as request input"]
#[inline(always)]
pub fn uart8_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::UART8_RX_DMA)
}
#[doc = "Signal `uart8_tx_dma` selected as request input"]
#[inline(always)]
pub fn uart8_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::UART8_TX_DMA)
}
#[doc = "Signal `spi4_rx_dma` selected as request input"]
#[inline(always)]
pub fn spi4_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI4_RX_DMA)
}
#[doc = "Signal `spi4_tx_dma` selected as request input"]
#[inline(always)]
pub fn spi4_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI4_TX_DMA)
}
#[doc = "Signal `spi5_rx_dma` selected as request input"]
#[inline(always)]
pub fn spi5_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI5_RX_DMA)
}
#[doc = "Signal `spi5_tx_dma` selected as request input"]
#[inline(always)]
pub fn spi5_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI5_TX_DMA)
}
#[doc = "Signal `sai1a_dma` selected as request input"]
#[inline(always)]
pub fn sai1a_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SAI1A_DMA)
}
#[doc = "Signal `sai1b_dma` selected as request input"]
#[inline(always)]
pub fn sai1b_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SAI1B_DMA)
}
#[doc = "Signal `sai2a_dma` selected as request input"]
#[inline(always)]
pub fn sai2a_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SAI2A_DMA)
}
#[doc = "Signal `sai2b_dma` selected as request input"]
#[inline(always)]
pub fn sai2b_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SAI2B_DMA)
}
#[doc = "Signal `swpmi_rx_dma` selected as request input"]
#[inline(always)]
pub fn swpmi_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SWPMI_RX_DMA)
}
#[doc = "Signal `swpmi_tx_dma` selected as request input"]
#[inline(always)]
pub fn swpmi_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SWPMI_TX_DMA)
}
#[doc = "Signal `spdifrx_dat_dma` selected as request input"]
#[inline(always)]
pub fn spdifrx_dat_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPDIFRX_DAT_DMA)
}
#[doc = "Signal `spdifrx_ctrl_dma` selected as request input"]
#[inline(always)]
pub fn spdifrx_ctrl_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPDIFRX_CTRL_DMA)
}
#[doc = "Signal `hr_req(1)` selected as request input"]
#[inline(always)]
pub fn hr_req1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::HR_REQ1)
}
#[doc = "Signal `hr_req(2)` selected as request input"]
#[inline(always)]
pub fn hr_req2(self) -> &'a mut W {
self.variant(DMAREQ_IDW::HR_REQ2)
}
#[doc = "Signal `hr_req(3)` selected as request input"]
#[inline(always)]
pub fn hr_req3(self) -> &'a mut W {
self.variant(DMAREQ_IDW::HR_REQ3)
}
#[doc = "Signal `hr_req(4)` selected as request input"]
#[inline(always)]
pub fn hr_req4(self) -> &'a mut W {
self.variant(DMAREQ_IDW::HR_REQ4)
}
#[doc = "Signal `hr_req(5)` selected as request input"]
#[inline(always)]
pub fn hr_req5(self) -> &'a mut W {
self.variant(DMAREQ_IDW::HR_REQ5)
}
#[doc = "Signal `hr_req(6)` selected as request input"]
#[inline(always)]
pub fn hr_req6(self) -> &'a mut W {
self.variant(DMAREQ_IDW::HR_REQ6)
}
#[doc = "Signal `dfsdm1_dma0` selected as request input"]
#[inline(always)]
pub fn dfsdm1_dma0(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DFSDM1_DMA0)
}
#[doc = "Signal `dfsdm1_dma1` selected as request input"]
#[inline(always)]
pub fn dfsdm1_dma1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DFSDM1_DMA1)
}
#[doc = "Signal `dfsdm1_dma2` selected as request input"]
#[inline(always)]
pub fn dfsdm1_dma2(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DFSDM1_DMA2)
}
#[doc = "Signal `dfsdm1_dma3` selected as request input"]
#[inline(always)]
pub fn dfsdm1_dma3(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DFSDM1_DMA3)
}
#[doc = "Signal `tim15_ch1` selected as request input"]
#[inline(always)]
pub fn tim15_ch1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM15_CH1)
}
#[doc = "Signal `tim15_up` selected as request input"]
#[inline(always)]
pub fn tim15_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM15_UP)
}
#[doc = "Signal `tim15_trig` selected as request input"]
#[inline(always)]
pub fn tim15_trig(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM15_TRIG)
}
#[doc = "Signal `tim15_com` selected as request input"]
#[inline(always)]
pub fn tim15_com(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM15_COM)
}
#[doc = "Signal `tim16_ch1` selected as request input"]
#[inline(always)]
pub fn tim16_ch1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM16_CH1)
}
#[doc = "Signal `tim16_up` selected as request input"]
#[inline(always)]
pub fn tim16_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM16_UP)
}
#[doc = "Signal `tim17_ch1` selected as request input"]
#[inline(always)]
pub fn tim17_ch1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM17_CH1)
}
#[doc = "Signal `tim17_up` selected as request input"]
#[inline(always)]
pub fn tim17_up(self) -> &'a mut W {
self.variant(DMAREQ_IDW::TIM17_UP)
}
#[doc = "Signal `sai3_a_dma` selected as request input"]
#[inline(always)]
pub fn sai3_a_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SAI3_A_DMA)
}
#[doc = "Signal `sai3_b_dma` selected as request input"]
#[inline(always)]
pub fn sai3_b_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SAI3_B_DMA)
}
#[doc = "Signal `adc3_dma` selected as request input"]
#[inline(always)]
pub fn adc3_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::ADC3_DMA)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0xff << 0);
self.w.bits |= ((value as u32) & 0xff) << 0;
self.w
}
}
#[doc = "Possible values of the field `SOIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOIER {
#[doc = "Synchronization overrun interrupt disabled"]
DISABLED,
#[doc = "Synchronization overrun interrupt enabled"]
ENABLED,
}
impl SOIER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SOIER::DISABLED => false,
SOIER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SOIER {
match value {
false => SOIER::DISABLED,
true => SOIER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SOIER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SOIER::ENABLED
}
}
#[doc = "Values that can be written to the field `SOIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOIEW {
#[doc = "Synchronization overrun interrupt disabled"]
DISABLED,
#[doc = "Synchronization overrun interrupt enabled"]
ENABLED,
}
impl SOIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SOIEW::DISABLED => false,
SOIEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SOIEW<'a> {
w: &'a mut W,
}
impl<'a> _SOIEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SOIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Synchronization overrun interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SOIEW::DISABLED)
}
#[doc = "Synchronization overrun interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SOIEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 8);
self.w.bits |= ((value as u32) & 0x01) << 8;
self.w
}
}
#[doc = "Possible values of the field `EGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EGER {
#[doc = "Event generation disabled"]
DISABLED,
#[doc = "Event generation enabled"]
ENABLED,
}
impl EGER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
EGER::DISABLED => false,
EGER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> EGER {
match value {
false => EGER::DISABLED,
true => EGER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == EGER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == EGER::ENABLED
}
}
#[doc = "Values that can be written to the field `EGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EGEW {
#[doc = "Event generation disabled"]
DISABLED,
#[doc = "Event generation enabled"]
ENABLED,
}
impl EGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
EGEW::DISABLED => false,
EGEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _EGEW<'a> {
w: &'a mut W,
}
impl<'a> _EGEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: EGEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Event generation disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(EGEW::DISABLED)
}
#[doc = "Event generation enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(EGEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 9);
self.w.bits |= ((value as u32) & 0x01) << 9;
self.w
}
}
#[doc = "Possible values of the field `SE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SER {
#[doc = "Synchronization disabled"]
DISABLED,
#[doc = "Synchronization enabled"]
ENABLED,
}
impl SER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SER::DISABLED => false,
SER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SER {
match value {
false => SER::DISABLED,
true => SER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SER::ENABLED
}
}
#[doc = "Values that can be written to the field `SE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SEW {
#[doc = "Synchronization disabled"]
DISABLED,
#[doc = "Synchronization enabled"]
ENABLED,
}
impl SEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SEW::DISABLED => false,
SEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SEW<'a> {
w: &'a mut W,
}
impl<'a> _SEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Synchronization disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SEW::DISABLED)
}
#[doc = "Synchronization enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 16);
self.w.bits |= ((value as u32) & 0x01) << 16;
self.w
}
}
#[doc = "Possible values of the field `SPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPOLR {
#[doc = "No event, i.e. no synchronization nor detection"]
NOEDGE,
#[doc = "Rising edge"]
RISINGEDGE,
#[doc = "Falling edge"]
FALLINGEDGE,
#[doc = "Rising and falling edges"]
BOTHEDGES,
}
impl SPOLR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SPOLR::NOEDGE => 0,
SPOLR::RISINGEDGE => 0x01,
SPOLR::FALLINGEDGE => 0x02,
SPOLR::BOTHEDGES => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SPOLR {
match value {
0 => SPOLR::NOEDGE,
1 => SPOLR::RISINGEDGE,
2 => SPOLR::FALLINGEDGE,
3 => SPOLR::BOTHEDGES,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `NOEDGE`"]
#[inline(always)]
pub fn is_no_edge(&self) -> bool {
*self == SPOLR::NOEDGE
}
#[doc = "Checks if the value of the field is `RISINGEDGE`"]
#[inline(always)]
pub fn is_rising_edge(&self) -> bool {
*self == SPOLR::RISINGEDGE
}
#[doc = "Checks if the value of the field is `FALLINGEDGE`"]
#[inline(always)]
pub fn is_falling_edge(&self) -> bool {
*self == SPOLR::FALLINGEDGE
}
#[doc = "Checks if the value of the field is `BOTHEDGES`"]
#[inline(always)]
pub fn is_both_edges(&self) -> bool {
*self == SPOLR::BOTHEDGES
}
}
#[doc = "Values that can be written to the field `SPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPOLW {
#[doc = "No event, i.e. no synchronization nor detection"]
NOEDGE,
#[doc = "Rising edge"]
RISINGEDGE,
#[doc = "Falling edge"]
FALLINGEDGE,
#[doc = "Rising and falling edges"]
BOTHEDGES,
}
impl SPOLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SPOLW::NOEDGE => 0,
SPOLW::RISINGEDGE => 1,
SPOLW::FALLINGEDGE => 2,
SPOLW::BOTHEDGES => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _SPOLW<'a> {
w: &'a mut W,
}
impl<'a> _SPOLW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SPOLW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "No event, i.e. no synchronization nor detection"]
#[inline(always)]
pub fn no_edge(self) -> &'a mut W {
self.variant(SPOLW::NOEDGE)
}
#[doc = "Rising edge"]
#[inline(always)]
pub fn rising_edge(self) -> &'a mut W {
self.variant(SPOLW::RISINGEDGE)
}
#[doc = "Falling edge"]
#[inline(always)]
pub fn falling_edge(self) -> &'a mut W {
self.variant(SPOLW::FALLINGEDGE)
}
#[doc = "Rising and falling edges"]
#[inline(always)]
pub fn both_edges(self) -> &'a mut W {
self.variant(SPOLW::BOTHEDGES)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 17);
self.w.bits |= ((value as u32) & 0x03) << 17;
self.w
}
}
#[doc = r"Value of the field"]
pub struct NBREQR {
bits: u8,
}
impl NBREQR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _NBREQW<'a> {
w: &'a mut W,
}
impl<'a> _NBREQW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 19);
self.w.bits |= ((value as u32) & 0x1f) << 19;
self.w
}
}
#[doc = "Possible values of the field `SYNC_ID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYNC_IDR {
#[doc = "Signal `dmamux1_evt0` selected as synchronization input"]
DMAMUX1_EVT0,
#[doc = "Signal `dmamux1_evt1` selected as synchronization input"]
DMAMUX1_EVT1,
#[doc = "Signal `dmamux1_evt2` selected as synchronization input"]
DMAMUX1_EVT2,
#[doc = "Signal `lptim1_out` selected as synchronization input"]
LPTIM1_OUT,
#[doc = "Signal `lptim2_out` selected as synchronization input"]
LPTIM2_OUT,
#[doc = "Signal `lptim3_out` selected as synchronization input"]
LPTIM3_OUT,
#[doc = "Signal `extit0` selected as synchronization input"]
EXTIT0,
#[doc = "Signal `tim12_trgo` selected as synchronization input"]
TIM12_TRGO,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl SYNC_IDR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SYNC_IDR::DMAMUX1_EVT0 => 0,
SYNC_IDR::DMAMUX1_EVT1 => 0x01,
SYNC_IDR::DMAMUX1_EVT2 => 0x02,
SYNC_IDR::LPTIM1_OUT => 0x03,
SYNC_IDR::LPTIM2_OUT => 0x04,
SYNC_IDR::LPTIM3_OUT => 0x05,
SYNC_IDR::EXTIT0 => 0x06,
SYNC_IDR::TIM12_TRGO => 0x07,
SYNC_IDR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SYNC_IDR {
match value {
0 => SYNC_IDR::DMAMUX1_EVT0,
1 => SYNC_IDR::DMAMUX1_EVT1,
2 => SYNC_IDR::DMAMUX1_EVT2,
3 => SYNC_IDR::LPTIM1_OUT,
4 => SYNC_IDR::LPTIM2_OUT,
5 => SYNC_IDR::LPTIM3_OUT,
6 => SYNC_IDR::EXTIT0,
7 => SYNC_IDR::TIM12_TRGO,
i => SYNC_IDR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `DMAMUX1_EVT0`"]
#[inline(always)]
pub fn is_dmamux1_evt0(&self) -> bool {
*self == SYNC_IDR::DMAMUX1_EVT0
}
#[doc = "Checks if the value of the field is `DMAMUX1_EVT1`"]
#[inline(always)]
pub fn is_dmamux1_evt1(&self) -> bool {
*self == SYNC_IDR::DMAMUX1_EVT1
}
#[doc = "Checks if the value of the field is `DMAMUX1_EVT2`"]
#[inline(always)]
pub fn is_dmamux1_evt2(&self) -> bool {
*self == SYNC_IDR::DMAMUX1_EVT2
}
#[doc = "Checks if the value of the field is `LPTIM1_OUT`"]
#[inline(always)]
pub fn is_lptim1_out(&self) -> bool {
*self == SYNC_IDR::LPTIM1_OUT
}
#[doc = "Checks if the value of the field is `LPTIM2_OUT`"]
#[inline(always)]
pub fn is_lptim2_out(&self) -> bool {
*self == SYNC_IDR::LPTIM2_OUT
}
#[doc = "Checks if the value of the field is `LPTIM3_OUT`"]
#[inline(always)]
pub fn is_lptim3_out(&self) -> bool {
*self == SYNC_IDR::LPTIM3_OUT
}
#[doc = "Checks if the value of the field is `EXTIT0`"]
#[inline(always)]
pub fn is_extit0(&self) -> bool {
*self == SYNC_IDR::EXTIT0
}
#[doc = "Checks if the value of the field is `TIM12_TRGO`"]
#[inline(always)]
pub fn is_tim12_trgo(&self) -> bool {
*self == SYNC_IDR::TIM12_TRGO
}
}
#[doc = "Values that can be written to the field `SYNC_ID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYNC_IDW {
#[doc = "Signal `dmamux1_evt0` selected as synchronization input"]
DMAMUX1_EVT0,
#[doc = "Signal `dmamux1_evt1` selected as synchronization input"]
DMAMUX1_EVT1,
#[doc = "Signal `dmamux1_evt2` selected as synchronization input"]
DMAMUX1_EVT2,
#[doc = "Signal `lptim1_out` selected as synchronization input"]
LPTIM1_OUT,
#[doc = "Signal `lptim2_out` selected as synchronization input"]
LPTIM2_OUT,
#[doc = "Signal `lptim3_out` selected as synchronization input"]
LPTIM3_OUT,
#[doc = "Signal `extit0` selected as synchronization input"]
EXTIT0,
#[doc = "Signal `tim12_trgo` selected as synchronization input"]
TIM12_TRGO,
}
impl SYNC_IDW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SYNC_IDW::DMAMUX1_EVT0 => 0,
SYNC_IDW::DMAMUX1_EVT1 => 1,
SYNC_IDW::DMAMUX1_EVT2 => 2,
SYNC_IDW::LPTIM1_OUT => 3,
SYNC_IDW::LPTIM2_OUT => 4,
SYNC_IDW::LPTIM3_OUT => 5,
SYNC_IDW::EXTIT0 => 6,
SYNC_IDW::TIM12_TRGO => 7,
}
}
}
#[doc = r"Proxy"]
pub struct _SYNC_IDW<'a> {
w: &'a mut W,
}
impl<'a> _SYNC_IDW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SYNC_IDW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Signal `dmamux1_evt0` selected as synchronization input"]
#[inline(always)]
pub fn dmamux1_evt0(self) -> &'a mut W {
self.variant(SYNC_IDW::DMAMUX1_EVT0)
}
#[doc = "Signal `dmamux1_evt1` selected as synchronization input"]
#[inline(always)]
pub fn dmamux1_evt1(self) -> &'a mut W {
self.variant(SYNC_IDW::DMAMUX1_EVT1)
}
#[doc = "Signal `dmamux1_evt2` selected as synchronization input"]
#[inline(always)]
pub fn dmamux1_evt2(self) -> &'a mut W {
self.variant(SYNC_IDW::DMAMUX1_EVT2)
}
#[doc = "Signal `lptim1_out` selected as synchronization input"]
#[inline(always)]
pub fn lptim1_out(self) -> &'a mut W {
self.variant(SYNC_IDW::LPTIM1_OUT)
}
#[doc = "Signal `lptim2_out` selected as synchronization input"]
#[inline(always)]
pub fn lptim2_out(self) -> &'a mut W {
self.variant(SYNC_IDW::LPTIM2_OUT)
}
#[doc = "Signal `lptim3_out` selected as synchronization input"]
#[inline(always)]
pub fn lptim3_out(self) -> &'a mut W {
self.variant(SYNC_IDW::LPTIM3_OUT)
}
#[doc = "Signal `extit0` selected as synchronization input"]
#[inline(always)]
pub fn extit0(self) -> &'a mut W {
self.variant(SYNC_IDW::EXTIT0)
}
#[doc = "Signal `tim12_trgo` selected as synchronization input"]
#[inline(always)]
pub fn tim12_trgo(self) -> &'a mut W {
self.variant(SYNC_IDW::TIM12_TRGO)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 24);
self.w.bits |= ((value as u32) & 0x1f) << 24;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Input DMA request line selected"]
#[inline(always)]
pub fn dmareq_id(&self) -> DMAREQ_IDR {
DMAREQ_IDR::_from(((self.bits >> 0) & 0xff) as u8)
}
#[doc = "Bit 8 - Interrupt enable at synchronization event overrun"]
#[inline(always)]
pub fn soie(&self) -> SOIER {
SOIER::_from(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 9 - Event generation enable/disable"]
#[inline(always)]
pub fn ege(&self) -> EGER {
EGER::_from(((self.bits >> 9) & 0x01) != 0)
}
#[doc = "Bit 16 - Synchronous operating mode enable/disable"]
#[inline(always)]
pub fn se(&self) -> SER {
SER::_from(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:"]
#[inline(always)]
pub fn spol(&self) -> SPOLR {
SPOLR::_from(((self.bits >> 17) & 0x03) as u8)
}
#[doc = "Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset."]
#[inline(always)]
pub fn nbreq(&self) -> NBREQR {
let bits = ((self.bits >> 19) & 0x1f) as u8;
NBREQR { bits }
}
#[doc = "Bits 24:28 - Synchronization input selected"]
#[inline(always)]
pub fn sync_id(&self) -> SYNC_IDR {
SYNC_IDR::_from(((self.bits >> 24) & 0x1f) as u8)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Input DMA request line selected"]
#[inline(always)]
pub fn dmareq_id(&mut self) -> _DMAREQ_IDW {
_DMAREQ_IDW { w: self }
}
#[doc = "Bit 8 - Interrupt enable at synchronization event overrun"]
#[inline(always)]
pub fn soie(&mut self) -> _SOIEW {
_SOIEW { w: self }
}
#[doc = "Bit 9 - Event generation enable/disable"]
#[inline(always)]
pub fn ege(&mut self) -> _EGEW {
_EGEW { w: self }
}
#[doc = "Bit 16 - Synchronous operating mode enable/disable"]
#[inline(always)]
pub fn se(&mut self) -> _SEW {
_SEW { w: self }
}
#[doc = "Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:"]
#[inline(always)]
pub fn spol(&mut self) -> _SPOLW {
_SPOLW { w: self }
}
#[doc = "Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset."]
#[inline(always)]
pub fn nbreq(&mut self) -> _NBREQW {
_NBREQW { w: self }
}
#[doc = "Bits 24:28 - Synchronization input selected"]
#[inline(always)]
pub fn sync_id(&mut self) -> _SYNC_IDW {
_SYNC_IDW { w: self }
}
}