#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFG1 {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0x0007_0007
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `MBR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MBRR {
#[doc = "f_spi_ker_ck / 2"]
DIV2,
#[doc = "f_spi_ker_ck / 4"]
DIV4,
#[doc = "f_spi_ker_ck / 8"]
DIV8,
#[doc = "f_spi_ker_ck / 16"]
DIV16,
#[doc = "f_spi_ker_ck / 32"]
DIV32,
#[doc = "f_spi_ker_ck / 64"]
DIV64,
#[doc = "f_spi_ker_ck / 128"]
DIV128,
#[doc = "f_spi_ker_ck / 256"]
DIV256,
}
impl MBRR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
MBRR::DIV2 => 0,
MBRR::DIV4 => 0x01,
MBRR::DIV8 => 0x02,
MBRR::DIV16 => 0x03,
MBRR::DIV32 => 0x04,
MBRR::DIV64 => 0x05,
MBRR::DIV128 => 0x06,
MBRR::DIV256 => 0x07,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> MBRR {
match value {
0 => MBRR::DIV2,
1 => MBRR::DIV4,
2 => MBRR::DIV8,
3 => MBRR::DIV16,
4 => MBRR::DIV32,
5 => MBRR::DIV64,
6 => MBRR::DIV128,
7 => MBRR::DIV256,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `DIV2`"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == MBRR::DIV2
}
#[doc = "Checks if the value of the field is `DIV4`"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == MBRR::DIV4
}
#[doc = "Checks if the value of the field is `DIV8`"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == MBRR::DIV8
}
#[doc = "Checks if the value of the field is `DIV16`"]
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == MBRR::DIV16
}
#[doc = "Checks if the value of the field is `DIV32`"]
#[inline(always)]
pub fn is_div32(&self) -> bool {
*self == MBRR::DIV32
}
#[doc = "Checks if the value of the field is `DIV64`"]
#[inline(always)]
pub fn is_div64(&self) -> bool {
*self == MBRR::DIV64
}
#[doc = "Checks if the value of the field is `DIV128`"]
#[inline(always)]
pub fn is_div128(&self) -> bool {
*self == MBRR::DIV128
}
#[doc = "Checks if the value of the field is `DIV256`"]
#[inline(always)]
pub fn is_div256(&self) -> bool {
*self == MBRR::DIV256
}
}
#[doc = "Values that can be written to the field `MBR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MBRW {
#[doc = "f_spi_ker_ck / 2"]
DIV2,
#[doc = "f_spi_ker_ck / 4"]
DIV4,
#[doc = "f_spi_ker_ck / 8"]
DIV8,
#[doc = "f_spi_ker_ck / 16"]
DIV16,
#[doc = "f_spi_ker_ck / 32"]
DIV32,
#[doc = "f_spi_ker_ck / 64"]
DIV64,
#[doc = "f_spi_ker_ck / 128"]
DIV128,
#[doc = "f_spi_ker_ck / 256"]
DIV256,
}
impl MBRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
MBRW::DIV2 => 0,
MBRW::DIV4 => 1,
MBRW::DIV8 => 2,
MBRW::DIV16 => 3,
MBRW::DIV32 => 4,
MBRW::DIV64 => 5,
MBRW::DIV128 => 6,
MBRW::DIV256 => 7,
}
}
}
#[doc = r"Proxy"]
pub struct _MBRW<'a> {
w: &'a mut W,
}
impl<'a> _MBRW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MBRW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "f_spi_ker_ck / 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut W {
self.variant(MBRW::DIV2)
}
#[doc = "f_spi_ker_ck / 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut W {
self.variant(MBRW::DIV4)
}
#[doc = "f_spi_ker_ck / 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut W {
self.variant(MBRW::DIV8)
}
#[doc = "f_spi_ker_ck / 16"]
#[inline(always)]
pub fn div16(self) -> &'a mut W {
self.variant(MBRW::DIV16)
}
#[doc = "f_spi_ker_ck / 32"]
#[inline(always)]
pub fn div32(self) -> &'a mut W {
self.variant(MBRW::DIV32)
}
#[doc = "f_spi_ker_ck / 64"]
#[inline(always)]
pub fn div64(self) -> &'a mut W {
self.variant(MBRW::DIV64)
}
#[doc = "f_spi_ker_ck / 128"]
#[inline(always)]
pub fn div128(self) -> &'a mut W {
self.variant(MBRW::DIV128)
}
#[doc = "f_spi_ker_ck / 256"]
#[inline(always)]
pub fn div256(self) -> &'a mut W {
self.variant(MBRW::DIV256)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 28);
self.w.bits |= ((value as u32) & 0x07) << 28;
self.w
}
}
#[doc = "Possible values of the field `CRCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CRCENR {
#[doc = "CRC calculation disabled"]
DISABLED,
#[doc = "CRC calculation enabled"]
ENABLED,
}
impl CRCENR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
CRCENR::DISABLED => false,
CRCENR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> CRCENR {
match value {
false => CRCENR::DISABLED,
true => CRCENR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == CRCENR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == CRCENR::ENABLED
}
}
#[doc = "Values that can be written to the field `CRCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CRCENW {
#[doc = "CRC calculation disabled"]
DISABLED,
#[doc = "CRC calculation enabled"]
ENABLED,
}
impl CRCENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CRCENW::DISABLED => false,
CRCENW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CRCENW<'a> {
w: &'a mut W,
}
impl<'a> _CRCENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CRCENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "CRC calculation disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(CRCENW::DISABLED)
}
#[doc = "CRC calculation enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(CRCENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 22);
self.w.bits |= ((value as u32) & 0x01) << 22;
self.w
}
}
#[doc = r"Value of the field"]
pub struct CRCSIZER {
bits: u8,
}
impl CRCSIZER {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _CRCSIZEW<'a> {
w: &'a mut W,
}
impl<'a> _CRCSIZEW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 16);
self.w.bits |= ((value as u32) & 0x1f) << 16;
self.w
}
}
#[doc = "Possible values of the field `TXDMAEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TXDMAENR {
#[doc = "Tx buffer DMA disabled"]
DISABLED,
#[doc = "Tx buffer DMA enabled"]
ENABLED,
}
impl TXDMAENR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
TXDMAENR::DISABLED => false,
TXDMAENR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> TXDMAENR {
match value {
false => TXDMAENR::DISABLED,
true => TXDMAENR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == TXDMAENR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == TXDMAENR::ENABLED
}
}
#[doc = "Values that can be written to the field `TXDMAEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TXDMAENW {
#[doc = "Tx buffer DMA disabled"]
DISABLED,
#[doc = "Tx buffer DMA enabled"]
ENABLED,
}
impl TXDMAENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
TXDMAENW::DISABLED => false,
TXDMAENW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _TXDMAENW<'a> {
w: &'a mut W,
}
impl<'a> _TXDMAENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TXDMAENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Tx buffer DMA disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(TXDMAENW::DISABLED)
}
#[doc = "Tx buffer DMA enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(TXDMAENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 15);
self.w.bits |= ((value as u32) & 0x01) << 15;
self.w
}
}
#[doc = "Possible values of the field `RXDMAEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXDMAENR {
#[doc = "Rx buffer DMA disabled"]
DISABLED,
#[doc = "Rx buffer DMA enabled"]
ENABLED,
}
impl RXDMAENR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
RXDMAENR::DISABLED => false,
RXDMAENR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> RXDMAENR {
match value {
false => RXDMAENR::DISABLED,
true => RXDMAENR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == RXDMAENR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == RXDMAENR::ENABLED
}
}
#[doc = "Values that can be written to the field `RXDMAEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXDMAENW {
#[doc = "Rx buffer DMA disabled"]
DISABLED,
#[doc = "Rx buffer DMA enabled"]
ENABLED,
}
impl RXDMAENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
RXDMAENW::DISABLED => false,
RXDMAENW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _RXDMAENW<'a> {
w: &'a mut W,
}
impl<'a> _RXDMAENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: RXDMAENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Rx buffer DMA disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(RXDMAENW::DISABLED)
}
#[doc = "Rx buffer DMA enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(RXDMAENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 14);
self.w.bits |= ((value as u32) & 0x01) << 14;
self.w
}
}
#[doc = "Possible values of the field `UDRDET`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum UDRDETR {
#[doc = "Underrun is detected at begin of data frame"]
STARTOFFRAME,
#[doc = "Underrun is detected at end of last data frame"]
ENDOFFRAME,
#[doc = "Underrun is detected at begin of active SS signal"]
STARTOFSLAVESELECT,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl UDRDETR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
UDRDETR::STARTOFFRAME => 0,
UDRDETR::ENDOFFRAME => 0x01,
UDRDETR::STARTOFSLAVESELECT => 0x02,
UDRDETR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> UDRDETR {
match value {
0 => UDRDETR::STARTOFFRAME,
1 => UDRDETR::ENDOFFRAME,
2 => UDRDETR::STARTOFSLAVESELECT,
i => UDRDETR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `STARTOFFRAME`"]
#[inline(always)]
pub fn is_start_of_frame(&self) -> bool {
*self == UDRDETR::STARTOFFRAME
}
#[doc = "Checks if the value of the field is `ENDOFFRAME`"]
#[inline(always)]
pub fn is_end_of_frame(&self) -> bool {
*self == UDRDETR::ENDOFFRAME
}
#[doc = "Checks if the value of the field is `STARTOFSLAVESELECT`"]
#[inline(always)]
pub fn is_start_of_slave_select(&self) -> bool {
*self == UDRDETR::STARTOFSLAVESELECT
}
}
#[doc = "Values that can be written to the field `UDRDET`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum UDRDETW {
#[doc = "Underrun is detected at begin of data frame"]
STARTOFFRAME,
#[doc = "Underrun is detected at end of last data frame"]
ENDOFFRAME,
#[doc = "Underrun is detected at begin of active SS signal"]
STARTOFSLAVESELECT,
}
impl UDRDETW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
UDRDETW::STARTOFFRAME => 0,
UDRDETW::ENDOFFRAME => 1,
UDRDETW::STARTOFSLAVESELECT => 2,
}
}
}
#[doc = r"Proxy"]
pub struct _UDRDETW<'a> {
w: &'a mut W,
}
impl<'a> _UDRDETW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: UDRDETW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Underrun is detected at begin of data frame"]
#[inline(always)]
pub fn start_of_frame(self) -> &'a mut W {
self.variant(UDRDETW::STARTOFFRAME)
}
#[doc = "Underrun is detected at end of last data frame"]
#[inline(always)]
pub fn end_of_frame(self) -> &'a mut W {
self.variant(UDRDETW::ENDOFFRAME)
}
#[doc = "Underrun is detected at begin of active SS signal"]
#[inline(always)]
pub fn start_of_slave_select(self) -> &'a mut W {
self.variant(UDRDETW::STARTOFSLAVESELECT)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 11);
self.w.bits |= ((value as u32) & 0x03) << 11;
self.w
}
}
#[doc = "Possible values of the field `UDRCFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum UDRCFGR {
#[doc = "Slave sends a constant underrun pattern"]
CONSTANT,
#[doc = "Slave repeats last received data frame from master"]
REPEATRECEIVED,
#[doc = "Slave repeats last transmitted data frame"]
REPEATTRANSMITTED,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl UDRCFGR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
UDRCFGR::CONSTANT => 0,
UDRCFGR::REPEATRECEIVED => 0x01,
UDRCFGR::REPEATTRANSMITTED => 0x02,
UDRCFGR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> UDRCFGR {
match value {
0 => UDRCFGR::CONSTANT,
1 => UDRCFGR::REPEATRECEIVED,
2 => UDRCFGR::REPEATTRANSMITTED,
i => UDRCFGR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `CONSTANT`"]
#[inline(always)]
pub fn is_constant(&self) -> bool {
*self == UDRCFGR::CONSTANT
}
#[doc = "Checks if the value of the field is `REPEATRECEIVED`"]
#[inline(always)]
pub fn is_repeat_received(&self) -> bool {
*self == UDRCFGR::REPEATRECEIVED
}
#[doc = "Checks if the value of the field is `REPEATTRANSMITTED`"]
#[inline(always)]
pub fn is_repeat_transmitted(&self) -> bool {
*self == UDRCFGR::REPEATTRANSMITTED
}
}
#[doc = "Values that can be written to the field `UDRCFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum UDRCFGW {
#[doc = "Slave sends a constant underrun pattern"]
CONSTANT,
#[doc = "Slave repeats last received data frame from master"]
REPEATRECEIVED,
#[doc = "Slave repeats last transmitted data frame"]
REPEATTRANSMITTED,
}
impl UDRCFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
UDRCFGW::CONSTANT => 0,
UDRCFGW::REPEATRECEIVED => 1,
UDRCFGW::REPEATTRANSMITTED => 2,
}
}
}
#[doc = r"Proxy"]
pub struct _UDRCFGW<'a> {
w: &'a mut W,
}
impl<'a> _UDRCFGW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: UDRCFGW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Slave sends a constant underrun pattern"]
#[inline(always)]
pub fn constant(self) -> &'a mut W {
self.variant(UDRCFGW::CONSTANT)
}
#[doc = "Slave repeats last received data frame from master"]
#[inline(always)]
pub fn repeat_received(self) -> &'a mut W {
self.variant(UDRCFGW::REPEATRECEIVED)
}
#[doc = "Slave repeats last transmitted data frame"]
#[inline(always)]
pub fn repeat_transmitted(self) -> &'a mut W {
self.variant(UDRCFGW::REPEATTRANSMITTED)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 9);
self.w.bits |= ((value as u32) & 0x03) << 9;
self.w
}
}
#[doc = "Possible values of the field `FTHLV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTHLVR {
#[doc = "1 frame"]
ONEFRAME,
#[doc = "2 frames"]
TWOFRAMES,
#[doc = "3 frames"]
THREEFRAMES,
#[doc = "4 frames"]
FOURFRAMES,
#[doc = "5 frames"]
FIVEFRAMES,
#[doc = "6 frames"]
SIXFRAMES,
#[doc = "7 frames"]
SEVENFRAMES,
#[doc = "8 frames"]
EIGHTFRAMES,
#[doc = "9 frames"]
NINEFRAMES,
#[doc = "10 frames"]
TENFRAMES,
#[doc = "11 frames"]
ELEVENFRAMES,
#[doc = "12 frames"]
TWELVEFRAMES,
#[doc = "13 frames"]
THIRTEENFRAMES,
#[doc = "14 frames"]
FOURTEENFRAMES,
#[doc = "15 frames"]
FIFTEENFRAMES,
#[doc = "16 frames"]
SIXTEENFRAMES,
}
impl FTHLVR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
FTHLVR::ONEFRAME => 0,
FTHLVR::TWOFRAMES => 0x01,
FTHLVR::THREEFRAMES => 0x02,
FTHLVR::FOURFRAMES => 0x03,
FTHLVR::FIVEFRAMES => 0x04,
FTHLVR::SIXFRAMES => 0x05,
FTHLVR::SEVENFRAMES => 0x06,
FTHLVR::EIGHTFRAMES => 0x07,
FTHLVR::NINEFRAMES => 0x08,
FTHLVR::TENFRAMES => 0x09,
FTHLVR::ELEVENFRAMES => 0x0a,
FTHLVR::TWELVEFRAMES => 0x0b,
FTHLVR::THIRTEENFRAMES => 0x0c,
FTHLVR::FOURTEENFRAMES => 0x0d,
FTHLVR::FIFTEENFRAMES => 0x0e,
FTHLVR::SIXTEENFRAMES => 0x0f,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> FTHLVR {
match value {
0 => FTHLVR::ONEFRAME,
1 => FTHLVR::TWOFRAMES,
2 => FTHLVR::THREEFRAMES,
3 => FTHLVR::FOURFRAMES,
4 => FTHLVR::FIVEFRAMES,
5 => FTHLVR::SIXFRAMES,
6 => FTHLVR::SEVENFRAMES,
7 => FTHLVR::EIGHTFRAMES,
8 => FTHLVR::NINEFRAMES,
9 => FTHLVR::TENFRAMES,
10 => FTHLVR::ELEVENFRAMES,
11 => FTHLVR::TWELVEFRAMES,
12 => FTHLVR::THIRTEENFRAMES,
13 => FTHLVR::FOURTEENFRAMES,
14 => FTHLVR::FIFTEENFRAMES,
15 => FTHLVR::SIXTEENFRAMES,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `ONEFRAME`"]
#[inline(always)]
pub fn is_one_frame(&self) -> bool {
*self == FTHLVR::ONEFRAME
}
#[doc = "Checks if the value of the field is `TWOFRAMES`"]
#[inline(always)]
pub fn is_two_frames(&self) -> bool {
*self == FTHLVR::TWOFRAMES
}
#[doc = "Checks if the value of the field is `THREEFRAMES`"]
#[inline(always)]
pub fn is_three_frames(&self) -> bool {
*self == FTHLVR::THREEFRAMES
}
#[doc = "Checks if the value of the field is `FOURFRAMES`"]
#[inline(always)]
pub fn is_four_frames(&self) -> bool {
*self == FTHLVR::FOURFRAMES
}
#[doc = "Checks if the value of the field is `FIVEFRAMES`"]
#[inline(always)]
pub fn is_five_frames(&self) -> bool {
*self == FTHLVR::FIVEFRAMES
}
#[doc = "Checks if the value of the field is `SIXFRAMES`"]
#[inline(always)]
pub fn is_six_frames(&self) -> bool {
*self == FTHLVR::SIXFRAMES
}
#[doc = "Checks if the value of the field is `SEVENFRAMES`"]
#[inline(always)]
pub fn is_seven_frames(&self) -> bool {
*self == FTHLVR::SEVENFRAMES
}
#[doc = "Checks if the value of the field is `EIGHTFRAMES`"]
#[inline(always)]
pub fn is_eight_frames(&self) -> bool {
*self == FTHLVR::EIGHTFRAMES
}
#[doc = "Checks if the value of the field is `NINEFRAMES`"]
#[inline(always)]
pub fn is_nine_frames(&self) -> bool {
*self == FTHLVR::NINEFRAMES
}
#[doc = "Checks if the value of the field is `TENFRAMES`"]
#[inline(always)]
pub fn is_ten_frames(&self) -> bool {
*self == FTHLVR::TENFRAMES
}
#[doc = "Checks if the value of the field is `ELEVENFRAMES`"]
#[inline(always)]
pub fn is_eleven_frames(&self) -> bool {
*self == FTHLVR::ELEVENFRAMES
}
#[doc = "Checks if the value of the field is `TWELVEFRAMES`"]
#[inline(always)]
pub fn is_twelve_frames(&self) -> bool {
*self == FTHLVR::TWELVEFRAMES
}
#[doc = "Checks if the value of the field is `THIRTEENFRAMES`"]
#[inline(always)]
pub fn is_thirteen_frames(&self) -> bool {
*self == FTHLVR::THIRTEENFRAMES
}
#[doc = "Checks if the value of the field is `FOURTEENFRAMES`"]
#[inline(always)]
pub fn is_fourteen_frames(&self) -> bool {
*self == FTHLVR::FOURTEENFRAMES
}
#[doc = "Checks if the value of the field is `FIFTEENFRAMES`"]
#[inline(always)]
pub fn is_fifteen_frames(&self) -> bool {
*self == FTHLVR::FIFTEENFRAMES
}
#[doc = "Checks if the value of the field is `SIXTEENFRAMES`"]
#[inline(always)]
pub fn is_sixteen_frames(&self) -> bool {
*self == FTHLVR::SIXTEENFRAMES
}
}
#[doc = "Values that can be written to the field `FTHLV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTHLVW {
#[doc = "1 frame"]
ONEFRAME,
#[doc = "2 frames"]
TWOFRAMES,
#[doc = "3 frames"]
THREEFRAMES,
#[doc = "4 frames"]
FOURFRAMES,
#[doc = "5 frames"]
FIVEFRAMES,
#[doc = "6 frames"]
SIXFRAMES,
#[doc = "7 frames"]
SEVENFRAMES,
#[doc = "8 frames"]
EIGHTFRAMES,
#[doc = "9 frames"]
NINEFRAMES,
#[doc = "10 frames"]
TENFRAMES,
#[doc = "11 frames"]
ELEVENFRAMES,
#[doc = "12 frames"]
TWELVEFRAMES,
#[doc = "13 frames"]
THIRTEENFRAMES,
#[doc = "14 frames"]
FOURTEENFRAMES,
#[doc = "15 frames"]
FIFTEENFRAMES,
#[doc = "16 frames"]
SIXTEENFRAMES,
}
impl FTHLVW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
FTHLVW::ONEFRAME => 0,
FTHLVW::TWOFRAMES => 1,
FTHLVW::THREEFRAMES => 2,
FTHLVW::FOURFRAMES => 3,
FTHLVW::FIVEFRAMES => 4,
FTHLVW::SIXFRAMES => 5,
FTHLVW::SEVENFRAMES => 6,
FTHLVW::EIGHTFRAMES => 7,
FTHLVW::NINEFRAMES => 8,
FTHLVW::TENFRAMES => 9,
FTHLVW::ELEVENFRAMES => 10,
FTHLVW::TWELVEFRAMES => 11,
FTHLVW::THIRTEENFRAMES => 12,
FTHLVW::FOURTEENFRAMES => 13,
FTHLVW::FIFTEENFRAMES => 14,
FTHLVW::SIXTEENFRAMES => 15,
}
}
}
#[doc = r"Proxy"]
pub struct _FTHLVW<'a> {
w: &'a mut W,
}
impl<'a> _FTHLVW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FTHLVW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1 frame"]
#[inline(always)]
pub fn one_frame(self) -> &'a mut W {
self.variant(FTHLVW::ONEFRAME)
}
#[doc = "2 frames"]
#[inline(always)]
pub fn two_frames(self) -> &'a mut W {
self.variant(FTHLVW::TWOFRAMES)
}
#[doc = "3 frames"]
#[inline(always)]
pub fn three_frames(self) -> &'a mut W {
self.variant(FTHLVW::THREEFRAMES)
}
#[doc = "4 frames"]
#[inline(always)]
pub fn four_frames(self) -> &'a mut W {
self.variant(FTHLVW::FOURFRAMES)
}
#[doc = "5 frames"]
#[inline(always)]
pub fn five_frames(self) -> &'a mut W {
self.variant(FTHLVW::FIVEFRAMES)
}
#[doc = "6 frames"]
#[inline(always)]
pub fn six_frames(self) -> &'a mut W {
self.variant(FTHLVW::SIXFRAMES)
}
#[doc = "7 frames"]
#[inline(always)]
pub fn seven_frames(self) -> &'a mut W {
self.variant(FTHLVW::SEVENFRAMES)
}
#[doc = "8 frames"]
#[inline(always)]
pub fn eight_frames(self) -> &'a mut W {
self.variant(FTHLVW::EIGHTFRAMES)
}
#[doc = "9 frames"]
#[inline(always)]
pub fn nine_frames(self) -> &'a mut W {
self.variant(FTHLVW::NINEFRAMES)
}
#[doc = "10 frames"]
#[inline(always)]
pub fn ten_frames(self) -> &'a mut W {
self.variant(FTHLVW::TENFRAMES)
}
#[doc = "11 frames"]
#[inline(always)]
pub fn eleven_frames(self) -> &'a mut W {
self.variant(FTHLVW::ELEVENFRAMES)
}
#[doc = "12 frames"]
#[inline(always)]
pub fn twelve_frames(self) -> &'a mut W {
self.variant(FTHLVW::TWELVEFRAMES)
}
#[doc = "13 frames"]
#[inline(always)]
pub fn thirteen_frames(self) -> &'a mut W {
self.variant(FTHLVW::THIRTEENFRAMES)
}
#[doc = "14 frames"]
#[inline(always)]
pub fn fourteen_frames(self) -> &'a mut W {
self.variant(FTHLVW::FOURTEENFRAMES)
}
#[doc = "15 frames"]
#[inline(always)]
pub fn fifteen_frames(self) -> &'a mut W {
self.variant(FTHLVW::FIFTEENFRAMES)
}
#[doc = "16 frames"]
#[inline(always)]
pub fn sixteen_frames(self) -> &'a mut W {
self.variant(FTHLVW::SIXTEENFRAMES)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x0f << 5);
self.w.bits |= ((value as u32) & 0x0f) << 5;
self.w
}
}
#[doc = r"Value of the field"]
pub struct DSIZER {
bits: u8,
}
impl DSIZER {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _DSIZEW<'a> {
w: &'a mut W,
}
impl<'a> _DSIZEW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 0);
self.w.bits |= ((value as u32) & 0x1f) << 0;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 28:30 - Master baud rate"]
#[inline(always)]
pub fn mbr(&self) -> MBRR {
MBRR::_from(((self.bits >> 28) & 0x07) as u8)
}
#[doc = "Bit 22 - Hardware CRC computation enable"]
#[inline(always)]
pub fn crcen(&self) -> CRCENR {
CRCENR::_from(((self.bits >> 22) & 0x01) != 0)
}
#[doc = "Bits 16:20 - Length of CRC frame to be transacted and compared"]
#[inline(always)]
pub fn crcsize(&self) -> CRCSIZER {
let bits = ((self.bits >> 16) & 0x1f) as u8;
CRCSIZER { bits }
}
#[doc = "Bit 15 - Tx DMA stream enable"]
#[inline(always)]
pub fn txdmaen(&self) -> TXDMAENR {
TXDMAENR::_from(((self.bits >> 15) & 0x01) != 0)
}
#[doc = "Bit 14 - Rx DMA stream enable"]
#[inline(always)]
pub fn rxdmaen(&self) -> RXDMAENR {
RXDMAENR::_from(((self.bits >> 14) & 0x01) != 0)
}
#[doc = "Bits 11:12 - Detection of underrun condition at slave transmitter"]
#[inline(always)]
pub fn udrdet(&self) -> UDRDETR {
UDRDETR::_from(((self.bits >> 11) & 0x03) as u8)
}
#[doc = "Bits 9:10 - Behavior of slave transmitter at underrun condition"]
#[inline(always)]
pub fn udrcfg(&self) -> UDRCFGR {
UDRCFGR::_from(((self.bits >> 9) & 0x03) as u8)
}
#[doc = "Bits 5:8 - threshold level"]
#[inline(always)]
pub fn fthlv(&self) -> FTHLVR {
FTHLVR::_from(((self.bits >> 5) & 0x0f) as u8)
}
#[doc = "Bits 0:4 - Number of bits in at single SPI data frame"]
#[inline(always)]
pub fn dsize(&self) -> DSIZER {
let bits = ((self.bits >> 0) & 0x1f) as u8;
DSIZER { bits }
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 28:30 - Master baud rate"]
#[inline(always)]
pub fn mbr(&mut self) -> _MBRW {
_MBRW { w: self }
}
#[doc = "Bit 22 - Hardware CRC computation enable"]
#[inline(always)]
pub fn crcen(&mut self) -> _CRCENW {
_CRCENW { w: self }
}
#[doc = "Bits 16:20 - Length of CRC frame to be transacted and compared"]
#[inline(always)]
pub fn crcsize(&mut self) -> _CRCSIZEW {
_CRCSIZEW { w: self }
}
#[doc = "Bit 15 - Tx DMA stream enable"]
#[inline(always)]
pub fn txdmaen(&mut self) -> _TXDMAENW {
_TXDMAENW { w: self }
}
#[doc = "Bit 14 - Rx DMA stream enable"]
#[inline(always)]
pub fn rxdmaen(&mut self) -> _RXDMAENW {
_RXDMAENW { w: self }
}
#[doc = "Bits 11:12 - Detection of underrun condition at slave transmitter"]
#[inline(always)]
pub fn udrdet(&mut self) -> _UDRDETW {
_UDRDETW { w: self }
}
#[doc = "Bits 9:10 - Behavior of slave transmitter at underrun condition"]
#[inline(always)]
pub fn udrcfg(&mut self) -> _UDRCFGW {
_UDRCFGW { w: self }
}
#[doc = "Bits 5:8 - threshold level"]
#[inline(always)]
pub fn fthlv(&mut self) -> _FTHLVW {
_FTHLVW { w: self }
}
#[doc = "Bits 0:4 - Number of bits in at single SPI data frame"]
#[inline(always)]
pub fn dsize(&mut self) -> _DSIZEW {
_DSIZEW { w: self }
}
}