#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::D2CCIP2R {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `USART234578SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USART234578SELR {
#[doc = "rcc_pclk1 selected as peripheral clock"]
RCC_PCLK1,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl USART234578SELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
USART234578SELR::RCC_PCLK1 => 0,
USART234578SELR::PLL2_Q => 0x01,
USART234578SELR::PLL3_Q => 0x02,
USART234578SELR::HSI_KER => 0x03,
USART234578SELR::CSI_KER => 0x04,
USART234578SELR::LSE => 0x05,
USART234578SELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> USART234578SELR {
match value {
0 => USART234578SELR::RCC_PCLK1,
1 => USART234578SELR::PLL2_Q,
2 => USART234578SELR::PLL3_Q,
3 => USART234578SELR::HSI_KER,
4 => USART234578SELR::CSI_KER,
5 => USART234578SELR::LSE,
i => USART234578SELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `RCC_PCLK1`"]
#[inline(always)]
pub fn is_rcc_pclk1(&self) -> bool {
*self == USART234578SELR::RCC_PCLK1
}
#[doc = "Checks if the value of the field is `PLL2_Q`"]
#[inline(always)]
pub fn is_pll2_q(&self) -> bool {
*self == USART234578SELR::PLL2_Q
}
#[doc = "Checks if the value of the field is `PLL3_Q`"]
#[inline(always)]
pub fn is_pll3_q(&self) -> bool {
*self == USART234578SELR::PLL3_Q
}
#[doc = "Checks if the value of the field is `HSI_KER`"]
#[inline(always)]
pub fn is_hsi_ker(&self) -> bool {
*self == USART234578SELR::HSI_KER
}
#[doc = "Checks if the value of the field is `CSI_KER`"]
#[inline(always)]
pub fn is_csi_ker(&self) -> bool {
*self == USART234578SELR::CSI_KER
}
#[doc = "Checks if the value of the field is `LSE`"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == USART234578SELR::LSE
}
}
#[doc = "Values that can be written to the field `USART234578SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USART234578SELW {
#[doc = "rcc_pclk1 selected as peripheral clock"]
RCC_PCLK1,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
#[doc = "LSE selected as peripheral clock"]
LSE,
}
impl USART234578SELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
USART234578SELW::RCC_PCLK1 => 0,
USART234578SELW::PLL2_Q => 1,
USART234578SELW::PLL3_Q => 2,
USART234578SELW::HSI_KER => 3,
USART234578SELW::CSI_KER => 4,
USART234578SELW::LSE => 5,
}
}
}
#[doc = r"Proxy"]
pub struct _USART234578SELW<'a> {
w: &'a mut W,
}
impl<'a> _USART234578SELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USART234578SELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "rcc_pclk1 selected as peripheral clock"]
#[inline(always)]
pub fn rcc_pclk1(self) -> &'a mut W {
self.variant(USART234578SELW::RCC_PCLK1)
}
#[doc = "pll2_q selected as peripheral clock"]
#[inline(always)]
pub fn pll2_q(self) -> &'a mut W {
self.variant(USART234578SELW::PLL2_Q)
}
#[doc = "pll3_q selected as peripheral clock"]
#[inline(always)]
pub fn pll3_q(self) -> &'a mut W {
self.variant(USART234578SELW::PLL3_Q)
}
#[doc = "hsi_ker selected as peripheral clock"]
#[inline(always)]
pub fn hsi_ker(self) -> &'a mut W {
self.variant(USART234578SELW::HSI_KER)
}
#[doc = "csi_ker selected as peripheral clock"]
#[inline(always)]
pub fn csi_ker(self) -> &'a mut W {
self.variant(USART234578SELW::CSI_KER)
}
#[doc = "LSE selected as peripheral clock"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART234578SELW::LSE)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 0);
self.w.bits |= ((value as u32) & 0x07) << 0;
self.w
}
}
#[doc = "Possible values of the field `USART16SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USART16SELR {
#[doc = "rcc_pclk2 selected as peripheral clock"]
RCC_PCLK2,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl USART16SELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
USART16SELR::RCC_PCLK2 => 0,
USART16SELR::PLL2_Q => 0x01,
USART16SELR::PLL3_Q => 0x02,
USART16SELR::HSI_KER => 0x03,
USART16SELR::CSI_KER => 0x04,
USART16SELR::LSE => 0x05,
USART16SELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> USART16SELR {
match value {
0 => USART16SELR::RCC_PCLK2,
1 => USART16SELR::PLL2_Q,
2 => USART16SELR::PLL3_Q,
3 => USART16SELR::HSI_KER,
4 => USART16SELR::CSI_KER,
5 => USART16SELR::LSE,
i => USART16SELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `RCC_PCLK2`"]
#[inline(always)]
pub fn is_rcc_pclk2(&self) -> bool {
*self == USART16SELR::RCC_PCLK2
}
#[doc = "Checks if the value of the field is `PLL2_Q`"]
#[inline(always)]
pub fn is_pll2_q(&self) -> bool {
*self == USART16SELR::PLL2_Q
}
#[doc = "Checks if the value of the field is `PLL3_Q`"]
#[inline(always)]
pub fn is_pll3_q(&self) -> bool {
*self == USART16SELR::PLL3_Q
}
#[doc = "Checks if the value of the field is `HSI_KER`"]
#[inline(always)]
pub fn is_hsi_ker(&self) -> bool {
*self == USART16SELR::HSI_KER
}
#[doc = "Checks if the value of the field is `CSI_KER`"]
#[inline(always)]
pub fn is_csi_ker(&self) -> bool {
*self == USART16SELR::CSI_KER
}
#[doc = "Checks if the value of the field is `LSE`"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == USART16SELR::LSE
}
}
#[doc = "Values that can be written to the field `USART16SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USART16SELW {
#[doc = "rcc_pclk2 selected as peripheral clock"]
RCC_PCLK2,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
#[doc = "LSE selected as peripheral clock"]
LSE,
}
impl USART16SELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
USART16SELW::RCC_PCLK2 => 0,
USART16SELW::PLL2_Q => 1,
USART16SELW::PLL3_Q => 2,
USART16SELW::HSI_KER => 3,
USART16SELW::CSI_KER => 4,
USART16SELW::LSE => 5,
}
}
}
#[doc = r"Proxy"]
pub struct _USART16SELW<'a> {
w: &'a mut W,
}
impl<'a> _USART16SELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USART16SELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "rcc_pclk2 selected as peripheral clock"]
#[inline(always)]
pub fn rcc_pclk2(self) -> &'a mut W {
self.variant(USART16SELW::RCC_PCLK2)
}
#[doc = "pll2_q selected as peripheral clock"]
#[inline(always)]
pub fn pll2_q(self) -> &'a mut W {
self.variant(USART16SELW::PLL2_Q)
}
#[doc = "pll3_q selected as peripheral clock"]
#[inline(always)]
pub fn pll3_q(self) -> &'a mut W {
self.variant(USART16SELW::PLL3_Q)
}
#[doc = "hsi_ker selected as peripheral clock"]
#[inline(always)]
pub fn hsi_ker(self) -> &'a mut W {
self.variant(USART16SELW::HSI_KER)
}
#[doc = "csi_ker selected as peripheral clock"]
#[inline(always)]
pub fn csi_ker(self) -> &'a mut W {
self.variant(USART16SELW::CSI_KER)
}
#[doc = "LSE selected as peripheral clock"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART16SELW::LSE)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 3);
self.w.bits |= ((value as u32) & 0x07) << 3;
self.w
}
}
#[doc = "Possible values of the field `RNGSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RNGSELR {
#[doc = "HSI48 selected as peripheral clock"]
HSI48,
#[doc = "pll1_q selected as peripheral clock"]
PLL1_Q,
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = "LSI selected as peripheral clock"]
LSI,
}
impl RNGSELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
RNGSELR::HSI48 => 0,
RNGSELR::PLL1_Q => 0x01,
RNGSELR::LSE => 0x02,
RNGSELR::LSI => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> RNGSELR {
match value {
0 => RNGSELR::HSI48,
1 => RNGSELR::PLL1_Q,
2 => RNGSELR::LSE,
3 => RNGSELR::LSI,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `HSI48`"]
#[inline(always)]
pub fn is_hsi48(&self) -> bool {
*self == RNGSELR::HSI48
}
#[doc = "Checks if the value of the field is `PLL1_Q`"]
#[inline(always)]
pub fn is_pll1_q(&self) -> bool {
*self == RNGSELR::PLL1_Q
}
#[doc = "Checks if the value of the field is `LSE`"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == RNGSELR::LSE
}
#[doc = "Checks if the value of the field is `LSI`"]
#[inline(always)]
pub fn is_lsi(&self) -> bool {
*self == RNGSELR::LSI
}
}
#[doc = "Values that can be written to the field `RNGSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RNGSELW {
#[doc = "HSI48 selected as peripheral clock"]
HSI48,
#[doc = "pll1_q selected as peripheral clock"]
PLL1_Q,
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = "LSI selected as peripheral clock"]
LSI,
}
impl RNGSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
RNGSELW::HSI48 => 0,
RNGSELW::PLL1_Q => 1,
RNGSELW::LSE => 2,
RNGSELW::LSI => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _RNGSELW<'a> {
w: &'a mut W,
}
impl<'a> _RNGSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: RNGSELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "HSI48 selected as peripheral clock"]
#[inline(always)]
pub fn hsi48(self) -> &'a mut W {
self.variant(RNGSELW::HSI48)
}
#[doc = "pll1_q selected as peripheral clock"]
#[inline(always)]
pub fn pll1_q(self) -> &'a mut W {
self.variant(RNGSELW::PLL1_Q)
}
#[doc = "LSE selected as peripheral clock"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(RNGSELW::LSE)
}
#[doc = "LSI selected as peripheral clock"]
#[inline(always)]
pub fn lsi(self) -> &'a mut W {
self.variant(RNGSELW::LSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 8);
self.w.bits |= ((value as u32) & 0x03) << 8;
self.w
}
}
#[doc = "Possible values of the field `I2C123SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C123SELR {
#[doc = "rcc_pclk1 selected as peripheral clock"]
RCC_PCLK1,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
}
impl I2C123SELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
I2C123SELR::RCC_PCLK1 => 0,
I2C123SELR::PLL3_R => 0x01,
I2C123SELR::HSI_KER => 0x02,
I2C123SELR::CSI_KER => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> I2C123SELR {
match value {
0 => I2C123SELR::RCC_PCLK1,
1 => I2C123SELR::PLL3_R,
2 => I2C123SELR::HSI_KER,
3 => I2C123SELR::CSI_KER,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `RCC_PCLK1`"]
#[inline(always)]
pub fn is_rcc_pclk1(&self) -> bool {
*self == I2C123SELR::RCC_PCLK1
}
#[doc = "Checks if the value of the field is `PLL3_R`"]
#[inline(always)]
pub fn is_pll3_r(&self) -> bool {
*self == I2C123SELR::PLL3_R
}
#[doc = "Checks if the value of the field is `HSI_KER`"]
#[inline(always)]
pub fn is_hsi_ker(&self) -> bool {
*self == I2C123SELR::HSI_KER
}
#[doc = "Checks if the value of the field is `CSI_KER`"]
#[inline(always)]
pub fn is_csi_ker(&self) -> bool {
*self == I2C123SELR::CSI_KER
}
}
#[doc = "Values that can be written to the field `I2C123SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C123SELW {
#[doc = "rcc_pclk1 selected as peripheral clock"]
RCC_PCLK1,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
}
impl I2C123SELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
I2C123SELW::RCC_PCLK1 => 0,
I2C123SELW::PLL3_R => 1,
I2C123SELW::HSI_KER => 2,
I2C123SELW::CSI_KER => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _I2C123SELW<'a> {
w: &'a mut W,
}
impl<'a> _I2C123SELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2C123SELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "rcc_pclk1 selected as peripheral clock"]
#[inline(always)]
pub fn rcc_pclk1(self) -> &'a mut W {
self.variant(I2C123SELW::RCC_PCLK1)
}
#[doc = "pll3_r selected as peripheral clock"]
#[inline(always)]
pub fn pll3_r(self) -> &'a mut W {
self.variant(I2C123SELW::PLL3_R)
}
#[doc = "hsi_ker selected as peripheral clock"]
#[inline(always)]
pub fn hsi_ker(self) -> &'a mut W {
self.variant(I2C123SELW::HSI_KER)
}
#[doc = "csi_ker selected as peripheral clock"]
#[inline(always)]
pub fn csi_ker(self) -> &'a mut W {
self.variant(I2C123SELW::CSI_KER)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 12);
self.w.bits |= ((value as u32) & 0x03) << 12;
self.w
}
}
#[doc = "Possible values of the field `USBSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USBSELR {
#[doc = "Disable the kernel clock"]
DISABLE,
#[doc = "pll1_q selected as peripheral clock"]
PLL1_Q,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q,
#[doc = "HSI48 selected as peripheral clock"]
HSI48,
}
impl USBSELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
USBSELR::DISABLE => 0,
USBSELR::PLL1_Q => 0x01,
USBSELR::PLL3_Q => 0x02,
USBSELR::HSI48 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> USBSELR {
match value {
0 => USBSELR::DISABLE,
1 => USBSELR::PLL1_Q,
2 => USBSELR::PLL3_Q,
3 => USBSELR::HSI48,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == USBSELR::DISABLE
}
#[doc = "Checks if the value of the field is `PLL1_Q`"]
#[inline(always)]
pub fn is_pll1_q(&self) -> bool {
*self == USBSELR::PLL1_Q
}
#[doc = "Checks if the value of the field is `PLL3_Q`"]
#[inline(always)]
pub fn is_pll3_q(&self) -> bool {
*self == USBSELR::PLL3_Q
}
#[doc = "Checks if the value of the field is `HSI48`"]
#[inline(always)]
pub fn is_hsi48(&self) -> bool {
*self == USBSELR::HSI48
}
}
#[doc = "Values that can be written to the field `USBSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USBSELW {
#[doc = "Disable the kernel clock"]
DISABLE,
#[doc = "pll1_q selected as peripheral clock"]
PLL1_Q,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q,
#[doc = "HSI48 selected as peripheral clock"]
HSI48,
}
impl USBSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
USBSELW::DISABLE => 0,
USBSELW::PLL1_Q => 1,
USBSELW::PLL3_Q => 2,
USBSELW::HSI48 => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _USBSELW<'a> {
w: &'a mut W,
}
impl<'a> _USBSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USBSELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Disable the kernel clock"]
#[inline(always)]
pub fn disable(self) -> &'a mut W {
self.variant(USBSELW::DISABLE)
}
#[doc = "pll1_q selected as peripheral clock"]
#[inline(always)]
pub fn pll1_q(self) -> &'a mut W {
self.variant(USBSELW::PLL1_Q)
}
#[doc = "pll3_q selected as peripheral clock"]
#[inline(always)]
pub fn pll3_q(self) -> &'a mut W {
self.variant(USBSELW::PLL3_Q)
}
#[doc = "HSI48 selected as peripheral clock"]
#[inline(always)]
pub fn hsi48(self) -> &'a mut W {
self.variant(USBSELW::HSI48)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 20);
self.w.bits |= ((value as u32) & 0x03) << 20;
self.w
}
}
#[doc = "Possible values of the field `CECSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CECSELR {
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = "LSI selected as peripheral clock"]
LSI,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl CECSELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
CECSELR::LSE => 0,
CECSELR::LSI => 0x01,
CECSELR::CSI_KER => 0x02,
CECSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> CECSELR {
match value {
0 => CECSELR::LSE,
1 => CECSELR::LSI,
2 => CECSELR::CSI_KER,
i => CECSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `LSE`"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == CECSELR::LSE
}
#[doc = "Checks if the value of the field is `LSI`"]
#[inline(always)]
pub fn is_lsi(&self) -> bool {
*self == CECSELR::LSI
}
#[doc = "Checks if the value of the field is `CSI_KER`"]
#[inline(always)]
pub fn is_csi_ker(&self) -> bool {
*self == CECSELR::CSI_KER
}
}
#[doc = "Values that can be written to the field `CECSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CECSELW {
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = "LSI selected as peripheral clock"]
LSI,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
}
impl CECSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
CECSELW::LSE => 0,
CECSELW::LSI => 1,
CECSELW::CSI_KER => 2,
}
}
}
#[doc = r"Proxy"]
pub struct _CECSELW<'a> {
w: &'a mut W,
}
impl<'a> _CECSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CECSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "LSE selected as peripheral clock"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(CECSELW::LSE)
}
#[doc = "LSI selected as peripheral clock"]
#[inline(always)]
pub fn lsi(self) -> &'a mut W {
self.variant(CECSELW::LSI)
}
#[doc = "csi_ker selected as peripheral clock"]
#[inline(always)]
pub fn csi_ker(self) -> &'a mut W {
self.variant(CECSELW::CSI_KER)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 22);
self.w.bits |= ((value as u32) & 0x03) << 22;
self.w
}
}
#[doc = "Possible values of the field `LPTIM1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPTIM1SELR {
#[doc = "rcc_pclk1 selected as peripheral clock"]
RCC_PCLK1,
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R,
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = "LSI selected as peripheral clock"]
LSI,
#[doc = "PER selected as peripheral clock"]
PER,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl LPTIM1SELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
LPTIM1SELR::RCC_PCLK1 => 0,
LPTIM1SELR::PLL2_P => 0x01,
LPTIM1SELR::PLL3_R => 0x02,
LPTIM1SELR::LSE => 0x03,
LPTIM1SELR::LSI => 0x04,
LPTIM1SELR::PER => 0x05,
LPTIM1SELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> LPTIM1SELR {
match value {
0 => LPTIM1SELR::RCC_PCLK1,
1 => LPTIM1SELR::PLL2_P,
2 => LPTIM1SELR::PLL3_R,
3 => LPTIM1SELR::LSE,
4 => LPTIM1SELR::LSI,
5 => LPTIM1SELR::PER,
i => LPTIM1SELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `RCC_PCLK1`"]
#[inline(always)]
pub fn is_rcc_pclk1(&self) -> bool {
*self == LPTIM1SELR::RCC_PCLK1
}
#[doc = "Checks if the value of the field is `PLL2_P`"]
#[inline(always)]
pub fn is_pll2_p(&self) -> bool {
*self == LPTIM1SELR::PLL2_P
}
#[doc = "Checks if the value of the field is `PLL3_R`"]
#[inline(always)]
pub fn is_pll3_r(&self) -> bool {
*self == LPTIM1SELR::PLL3_R
}
#[doc = "Checks if the value of the field is `LSE`"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == LPTIM1SELR::LSE
}
#[doc = "Checks if the value of the field is `LSI`"]
#[inline(always)]
pub fn is_lsi(&self) -> bool {
*self == LPTIM1SELR::LSI
}
#[doc = "Checks if the value of the field is `PER`"]
#[inline(always)]
pub fn is_per(&self) -> bool {
*self == LPTIM1SELR::PER
}
}
#[doc = "Values that can be written to the field `LPTIM1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPTIM1SELW {
#[doc = "rcc_pclk1 selected as peripheral clock"]
RCC_PCLK1,
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R,
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = "LSI selected as peripheral clock"]
LSI,
#[doc = "PER selected as peripheral clock"]
PER,
}
impl LPTIM1SELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
LPTIM1SELW::RCC_PCLK1 => 0,
LPTIM1SELW::PLL2_P => 1,
LPTIM1SELW::PLL3_R => 2,
LPTIM1SELW::LSE => 3,
LPTIM1SELW::LSI => 4,
LPTIM1SELW::PER => 5,
}
}
}
#[doc = r"Proxy"]
pub struct _LPTIM1SELW<'a> {
w: &'a mut W,
}
impl<'a> _LPTIM1SELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: LPTIM1SELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "rcc_pclk1 selected as peripheral clock"]
#[inline(always)]
pub fn rcc_pclk1(self) -> &'a mut W {
self.variant(LPTIM1SELW::RCC_PCLK1)
}
#[doc = "pll2_p selected as peripheral clock"]
#[inline(always)]
pub fn pll2_p(self) -> &'a mut W {
self.variant(LPTIM1SELW::PLL2_P)
}
#[doc = "pll3_r selected as peripheral clock"]
#[inline(always)]
pub fn pll3_r(self) -> &'a mut W {
self.variant(LPTIM1SELW::PLL3_R)
}
#[doc = "LSE selected as peripheral clock"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(LPTIM1SELW::LSE)
}
#[doc = "LSI selected as peripheral clock"]
#[inline(always)]
pub fn lsi(self) -> &'a mut W {
self.variant(LPTIM1SELW::LSI)
}
#[doc = "PER selected as peripheral clock"]
#[inline(always)]
pub fn per(self) -> &'a mut W {
self.variant(LPTIM1SELW::PER)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 28);
self.w.bits |= ((value as u32) & 0x07) << 28;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection"]
#[inline(always)]
pub fn usart234578sel(&self) -> USART234578SELR {
USART234578SELR::_from(((self.bits >> 0) & 0x07) as u8)
}
#[doc = "Bits 3:5 - USART1 and 6 kernel clock source selection"]
#[inline(always)]
pub fn usart16sel(&self) -> USART16SELR {
USART16SELR::_from(((self.bits >> 3) & 0x07) as u8)
}
#[doc = "Bits 8:9 - RNG kernel clock source selection"]
#[inline(always)]
pub fn rngsel(&self) -> RNGSELR {
RNGSELR::_from(((self.bits >> 8) & 0x03) as u8)
}
#[doc = "Bits 12:13 - I2C1,2,3 kernel clock source selection"]
#[inline(always)]
pub fn i2c123sel(&self) -> I2C123SELR {
I2C123SELR::_from(((self.bits >> 12) & 0x03) as u8)
}
#[doc = "Bits 20:21 - USBOTG 1 and 2 kernel clock source selection"]
#[inline(always)]
pub fn usbsel(&self) -> USBSELR {
USBSELR::_from(((self.bits >> 20) & 0x03) as u8)
}
#[doc = "Bits 22:23 - HDMI-CEC kernel clock source selection"]
#[inline(always)]
pub fn cecsel(&self) -> CECSELR {
CECSELR::_from(((self.bits >> 22) & 0x03) as u8)
}
#[doc = "Bits 28:30 - LPTIM1 kernel clock source selection"]
#[inline(always)]
pub fn lptim1sel(&self) -> LPTIM1SELR {
LPTIM1SELR::_from(((self.bits >> 28) & 0x07) as u8)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection"]
#[inline(always)]
pub fn usart234578sel(&mut self) -> _USART234578SELW {
_USART234578SELW { w: self }
}
#[doc = "Bits 3:5 - USART1 and 6 kernel clock source selection"]
#[inline(always)]
pub fn usart16sel(&mut self) -> _USART16SELW {
_USART16SELW { w: self }
}
#[doc = "Bits 8:9 - RNG kernel clock source selection"]
#[inline(always)]
pub fn rngsel(&mut self) -> _RNGSELW {
_RNGSELW { w: self }
}
#[doc = "Bits 12:13 - I2C1,2,3 kernel clock source selection"]
#[inline(always)]
pub fn i2c123sel(&mut self) -> _I2C123SELW {
_I2C123SELW { w: self }
}
#[doc = "Bits 20:21 - USBOTG 1 and 2 kernel clock source selection"]
#[inline(always)]
pub fn usbsel(&mut self) -> _USBSELW {
_USBSELW { w: self }
}
#[doc = "Bits 22:23 - HDMI-CEC kernel clock source selection"]
#[inline(always)]
pub fn cecsel(&mut self) -> _CECSELW {
_CECSELW { w: self }
}
#[doc = "Bits 28:30 - LPTIM1 kernel clock source selection"]
#[inline(always)]
pub fn lptim1sel(&mut self) -> _LPTIM1SELW {
_LPTIM1SELW { w: self }
}
}