#[doc = r"Value read from the register"]
pub struct R {
    bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
    bits: u32,
}
impl super::D2CCIP1R {
    #[doc = r"Modifies the contents of the register"]
    #[inline(always)]
    pub fn modify<F>(&self, f: F)
    where
        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
    {
        let bits = self.register.get();
        self.register.set(f(&R { bits }, &mut W { bits }).bits);
    }
    #[doc = r"Reads the contents of the register"]
    #[inline(always)]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
    #[doc = r"Writes to the register"]
    #[inline(always)]
    pub fn write<F>(&self, f: F)
    where
        F: FnOnce(&mut W) -> &mut W,
    {
        self.register.set(
            f(&mut W {
                bits: Self::reset_value(),
            })
            .bits,
        );
    }
    #[doc = r"Reset value of the register"]
    #[inline(always)]
    pub const fn reset_value() -> u32 {
        0
    }
    #[doc = r"Writes the reset value to the register"]
    #[inline(always)]
    pub fn reset(&self) {
        self.register.set(Self::reset_value())
    }
}
#[doc = "Possible values of the field `SAI1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SAI1SELR {
    #[doc = "pll1_q selected as peripheral clock"]
    PLL1_Q,
    #[doc = "pll2_p selected as peripheral clock"]
    PLL2_P,
    #[doc = "pll3_p selected as peripheral clock"]
    PLL3_P,
    #[doc = "I2S_CKIN selected as peripheral clock"]
    I2S_CKIN,
    #[doc = "PER selected as peripheral clock"]
    PER,
    #[doc = r"Reserved"]
    _Reserved(u8),
}
impl SAI1SELR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        match *self {
            SAI1SELR::PLL1_Q => 0,
            SAI1SELR::PLL2_P => 0x01,
            SAI1SELR::PLL3_P => 0x02,
            SAI1SELR::I2S_CKIN => 0x03,
            SAI1SELR::PER => 0x04,
            SAI1SELR::_Reserved(bits) => bits,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _from(value: u8) -> SAI1SELR {
        match value {
            0 => SAI1SELR::PLL1_Q,
            1 => SAI1SELR::PLL2_P,
            2 => SAI1SELR::PLL3_P,
            3 => SAI1SELR::I2S_CKIN,
            4 => SAI1SELR::PER,
            i => SAI1SELR::_Reserved(i),
        }
    }
    #[doc = "Checks if the value of the field is `PLL1_Q`"]
    #[inline(always)]
    pub fn is_pll1_q(&self) -> bool {
        *self == SAI1SELR::PLL1_Q
    }
    #[doc = "Checks if the value of the field is `PLL2_P`"]
    #[inline(always)]
    pub fn is_pll2_p(&self) -> bool {
        *self == SAI1SELR::PLL2_P
    }
    #[doc = "Checks if the value of the field is `PLL3_P`"]
    #[inline(always)]
    pub fn is_pll3_p(&self) -> bool {
        *self == SAI1SELR::PLL3_P
    }
    #[doc = "Checks if the value of the field is `I2S_CKIN`"]
    #[inline(always)]
    pub fn is_i2s_ckin(&self) -> bool {
        *self == SAI1SELR::I2S_CKIN
    }
    #[doc = "Checks if the value of the field is `PER`"]
    #[inline(always)]
    pub fn is_per(&self) -> bool {
        *self == SAI1SELR::PER
    }
}
#[doc = "Values that can be written to the field `SAI1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SAI1SELW {
    #[doc = "pll1_q selected as peripheral clock"]
    PLL1_Q,
    #[doc = "pll2_p selected as peripheral clock"]
    PLL2_P,
    #[doc = "pll3_p selected as peripheral clock"]
    PLL3_P,
    #[doc = "I2S_CKIN selected as peripheral clock"]
    I2S_CKIN,
    #[doc = "PER selected as peripheral clock"]
    PER,
}
impl SAI1SELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _bits(&self) -> u8 {
        match *self {
            SAI1SELW::PLL1_Q => 0,
            SAI1SELW::PLL2_P => 1,
            SAI1SELW::PLL3_P => 2,
            SAI1SELW::I2S_CKIN => 3,
            SAI1SELW::PER => 4,
        }
    }
}
#[doc = r"Proxy"]
pub struct _SAI1SELW<'a> {
    w: &'a mut W,
}
impl<'a> _SAI1SELW<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SAI1SELW) -> &'a mut W {
        unsafe { self.bits(variant._bits()) }
    }
    #[doc = "pll1_q selected as peripheral clock"]
    #[inline(always)]
    pub fn pll1_q(self) -> &'a mut W {
        self.variant(SAI1SELW::PLL1_Q)
    }
    #[doc = "pll2_p selected as peripheral clock"]
    #[inline(always)]
    pub fn pll2_p(self) -> &'a mut W {
        self.variant(SAI1SELW::PLL2_P)
    }
    #[doc = "pll3_p selected as peripheral clock"]
    #[inline(always)]
    pub fn pll3_p(self) -> &'a mut W {
        self.variant(SAI1SELW::PLL3_P)
    }
    #[doc = "I2S_CKIN selected as peripheral clock"]
    #[inline(always)]
    pub fn i2s_ckin(self) -> &'a mut W {
        self.variant(SAI1SELW::I2S_CKIN)
    }
    #[doc = "PER selected as peripheral clock"]
    #[inline(always)]
    pub fn per(self) -> &'a mut W {
        self.variant(SAI1SELW::PER)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x07 << 0);
        self.w.bits |= ((value as u32) & 0x07) << 0;
        self.w
    }
}
#[doc = "Possible values of the field `SAI23SEL`"]
pub type SAI23SELR = SAI1SELR;
#[doc = "Values that can be written to the field `SAI23SEL`"]
pub type SAI23SELW = SAI1SELW;
#[doc = r"Proxy"]
pub struct _SAI23SELW<'a> {
    w: &'a mut W,
}
impl<'a> _SAI23SELW<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SAI23SELW) -> &'a mut W {
        unsafe { self.bits(variant._bits()) }
    }
    #[doc = "pll1_q selected as peripheral clock"]
    #[inline(always)]
    pub fn pll1_q(self) -> &'a mut W {
        self.variant(SAI1SELW::PLL1_Q)
    }
    #[doc = "pll2_p selected as peripheral clock"]
    #[inline(always)]
    pub fn pll2_p(self) -> &'a mut W {
        self.variant(SAI1SELW::PLL2_P)
    }
    #[doc = "pll3_p selected as peripheral clock"]
    #[inline(always)]
    pub fn pll3_p(self) -> &'a mut W {
        self.variant(SAI1SELW::PLL3_P)
    }
    #[doc = "I2S_CKIN selected as peripheral clock"]
    #[inline(always)]
    pub fn i2s_ckin(self) -> &'a mut W {
        self.variant(SAI1SELW::I2S_CKIN)
    }
    #[doc = "PER selected as peripheral clock"]
    #[inline(always)]
    pub fn per(self) -> &'a mut W {
        self.variant(SAI1SELW::PER)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x07 << 6);
        self.w.bits |= ((value as u32) & 0x07) << 6;
        self.w
    }
}
#[doc = "Possible values of the field `SPI123SEL`"]
pub type SPI123SELR = SAI1SELR;
#[doc = "Values that can be written to the field `SPI123SEL`"]
pub type SPI123SELW = SAI1SELW;
#[doc = r"Proxy"]
pub struct _SPI123SELW<'a> {
    w: &'a mut W,
}
impl<'a> _SPI123SELW<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SPI123SELW) -> &'a mut W {
        unsafe { self.bits(variant._bits()) }
    }
    #[doc = "pll1_q selected as peripheral clock"]
    #[inline(always)]
    pub fn pll1_q(self) -> &'a mut W {
        self.variant(SAI1SELW::PLL1_Q)
    }
    #[doc = "pll2_p selected as peripheral clock"]
    #[inline(always)]
    pub fn pll2_p(self) -> &'a mut W {
        self.variant(SAI1SELW::PLL2_P)
    }
    #[doc = "pll3_p selected as peripheral clock"]
    #[inline(always)]
    pub fn pll3_p(self) -> &'a mut W {
        self.variant(SAI1SELW::PLL3_P)
    }
    #[doc = "I2S_CKIN selected as peripheral clock"]
    #[inline(always)]
    pub fn i2s_ckin(self) -> &'a mut W {
        self.variant(SAI1SELW::I2S_CKIN)
    }
    #[doc = "PER selected as peripheral clock"]
    #[inline(always)]
    pub fn per(self) -> &'a mut W {
        self.variant(SAI1SELW::PER)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x07 << 12);
        self.w.bits |= ((value as u32) & 0x07) << 12;
        self.w
    }
}
#[doc = "Possible values of the field `SPI45SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPI45SELR {
    #[doc = "APB clock selected as peripheral clock"]
    APB,
    #[doc = "pll2_q selected as peripheral clock"]
    PLL2_Q,
    #[doc = "pll3_q selected as peripheral clock"]
    PLL3_Q,
    #[doc = "hsi_ker selected as peripheral clock"]
    HSI_KER,
    #[doc = "csi_ker selected as peripheral clock"]
    CSI_KER,
    #[doc = "HSE selected as peripheral clock"]
    HSE,
    #[doc = r"Reserved"]
    _Reserved(u8),
}
impl SPI45SELR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        match *self {
            SPI45SELR::APB => 0,
            SPI45SELR::PLL2_Q => 0x01,
            SPI45SELR::PLL3_Q => 0x02,
            SPI45SELR::HSI_KER => 0x03,
            SPI45SELR::CSI_KER => 0x04,
            SPI45SELR::HSE => 0x05,
            SPI45SELR::_Reserved(bits) => bits,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _from(value: u8) -> SPI45SELR {
        match value {
            0 => SPI45SELR::APB,
            1 => SPI45SELR::PLL2_Q,
            2 => SPI45SELR::PLL3_Q,
            3 => SPI45SELR::HSI_KER,
            4 => SPI45SELR::CSI_KER,
            5 => SPI45SELR::HSE,
            i => SPI45SELR::_Reserved(i),
        }
    }
    #[doc = "Checks if the value of the field is `APB`"]
    #[inline(always)]
    pub fn is_apb(&self) -> bool {
        *self == SPI45SELR::APB
    }
    #[doc = "Checks if the value of the field is `PLL2_Q`"]
    #[inline(always)]
    pub fn is_pll2_q(&self) -> bool {
        *self == SPI45SELR::PLL2_Q
    }
    #[doc = "Checks if the value of the field is `PLL3_Q`"]
    #[inline(always)]
    pub fn is_pll3_q(&self) -> bool {
        *self == SPI45SELR::PLL3_Q
    }
    #[doc = "Checks if the value of the field is `HSI_KER`"]
    #[inline(always)]
    pub fn is_hsi_ker(&self) -> bool {
        *self == SPI45SELR::HSI_KER
    }
    #[doc = "Checks if the value of the field is `CSI_KER`"]
    #[inline(always)]
    pub fn is_csi_ker(&self) -> bool {
        *self == SPI45SELR::CSI_KER
    }
    #[doc = "Checks if the value of the field is `HSE`"]
    #[inline(always)]
    pub fn is_hse(&self) -> bool {
        *self == SPI45SELR::HSE
    }
}
#[doc = "Values that can be written to the field `SPI45SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPI45SELW {
    #[doc = "APB clock selected as peripheral clock"]
    APB,
    #[doc = "pll2_q selected as peripheral clock"]
    PLL2_Q,
    #[doc = "pll3_q selected as peripheral clock"]
    PLL3_Q,
    #[doc = "hsi_ker selected as peripheral clock"]
    HSI_KER,
    #[doc = "csi_ker selected as peripheral clock"]
    CSI_KER,
    #[doc = "HSE selected as peripheral clock"]
    HSE,
}
impl SPI45SELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _bits(&self) -> u8 {
        match *self {
            SPI45SELW::APB => 0,
            SPI45SELW::PLL2_Q => 1,
            SPI45SELW::PLL3_Q => 2,
            SPI45SELW::HSI_KER => 3,
            SPI45SELW::CSI_KER => 4,
            SPI45SELW::HSE => 5,
        }
    }
}
#[doc = r"Proxy"]
pub struct _SPI45SELW<'a> {
    w: &'a mut W,
}
impl<'a> _SPI45SELW<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SPI45SELW) -> &'a mut W {
        unsafe { self.bits(variant._bits()) }
    }
    #[doc = "APB clock selected as peripheral clock"]
    #[inline(always)]
    pub fn apb(self) -> &'a mut W {
        self.variant(SPI45SELW::APB)
    }
    #[doc = "pll2_q selected as peripheral clock"]
    #[inline(always)]
    pub fn pll2_q(self) -> &'a mut W {
        self.variant(SPI45SELW::PLL2_Q)
    }
    #[doc = "pll3_q selected as peripheral clock"]
    #[inline(always)]
    pub fn pll3_q(self) -> &'a mut W {
        self.variant(SPI45SELW::PLL3_Q)
    }
    #[doc = "hsi_ker selected as peripheral clock"]
    #[inline(always)]
    pub fn hsi_ker(self) -> &'a mut W {
        self.variant(SPI45SELW::HSI_KER)
    }
    #[doc = "csi_ker selected as peripheral clock"]
    #[inline(always)]
    pub fn csi_ker(self) -> &'a mut W {
        self.variant(SPI45SELW::CSI_KER)
    }
    #[doc = "HSE selected as peripheral clock"]
    #[inline(always)]
    pub fn hse(self) -> &'a mut W {
        self.variant(SPI45SELW::HSE)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x07 << 16);
        self.w.bits |= ((value as u32) & 0x07) << 16;
        self.w
    }
}
#[doc = "Possible values of the field `SPDIFSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPDIFSELR {
    #[doc = "pll1_q selected as peripheral clock"]
    PLL1_Q,
    #[doc = "pll2_r selected as peripheral clock"]
    PLL2_R,
    #[doc = "pll3_r selected as peripheral clock"]
    PLL3_R,
    #[doc = "hsi_ker selected as peripheral clock"]
    HSI_KER,
}
impl SPDIFSELR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        match *self {
            SPDIFSELR::PLL1_Q => 0,
            SPDIFSELR::PLL2_R => 0x01,
            SPDIFSELR::PLL3_R => 0x02,
            SPDIFSELR::HSI_KER => 0x03,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _from(value: u8) -> SPDIFSELR {
        match value {
            0 => SPDIFSELR::PLL1_Q,
            1 => SPDIFSELR::PLL2_R,
            2 => SPDIFSELR::PLL3_R,
            3 => SPDIFSELR::HSI_KER,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `PLL1_Q`"]
    #[inline(always)]
    pub fn is_pll1_q(&self) -> bool {
        *self == SPDIFSELR::PLL1_Q
    }
    #[doc = "Checks if the value of the field is `PLL2_R`"]
    #[inline(always)]
    pub fn is_pll2_r(&self) -> bool {
        *self == SPDIFSELR::PLL2_R
    }
    #[doc = "Checks if the value of the field is `PLL3_R`"]
    #[inline(always)]
    pub fn is_pll3_r(&self) -> bool {
        *self == SPDIFSELR::PLL3_R
    }
    #[doc = "Checks if the value of the field is `HSI_KER`"]
    #[inline(always)]
    pub fn is_hsi_ker(&self) -> bool {
        *self == SPDIFSELR::HSI_KER
    }
}
#[doc = "Values that can be written to the field `SPDIFSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPDIFSELW {
    #[doc = "pll1_q selected as peripheral clock"]
    PLL1_Q,
    #[doc = "pll2_r selected as peripheral clock"]
    PLL2_R,
    #[doc = "pll3_r selected as peripheral clock"]
    PLL3_R,
    #[doc = "hsi_ker selected as peripheral clock"]
    HSI_KER,
}
impl SPDIFSELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _bits(&self) -> u8 {
        match *self {
            SPDIFSELW::PLL1_Q => 0,
            SPDIFSELW::PLL2_R => 1,
            SPDIFSELW::PLL3_R => 2,
            SPDIFSELW::HSI_KER => 3,
        }
    }
}
#[doc = r"Proxy"]
pub struct _SPDIFSELW<'a> {
    w: &'a mut W,
}
impl<'a> _SPDIFSELW<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SPDIFSELW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "pll1_q selected as peripheral clock"]
    #[inline(always)]
    pub fn pll1_q(self) -> &'a mut W {
        self.variant(SPDIFSELW::PLL1_Q)
    }
    #[doc = "pll2_r selected as peripheral clock"]
    #[inline(always)]
    pub fn pll2_r(self) -> &'a mut W {
        self.variant(SPDIFSELW::PLL2_R)
    }
    #[doc = "pll3_r selected as peripheral clock"]
    #[inline(always)]
    pub fn pll3_r(self) -> &'a mut W {
        self.variant(SPDIFSELW::PLL3_R)
    }
    #[doc = "hsi_ker selected as peripheral clock"]
    #[inline(always)]
    pub fn hsi_ker(self) -> &'a mut W {
        self.variant(SPDIFSELW::HSI_KER)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x03 << 20);
        self.w.bits |= ((value as u32) & 0x03) << 20;
        self.w
    }
}
#[doc = "Possible values of the field `DFSDM1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DFSDM1SELR {
    #[doc = "rcc_pclk2 selected as peripheral clock"]
    RCC_PCLK2,
    #[doc = "System clock selected as peripheral clock"]
    SYS,
}
impl DFSDM1SELR {
    #[doc = r"Returns `true` if the bit is clear (0)"]
    #[inline(always)]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r"Returns `true` if the bit is set (1)"]
    #[inline(always)]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bit(&self) -> bool {
        match *self {
            DFSDM1SELR::RCC_PCLK2 => false,
            DFSDM1SELR::SYS => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _from(value: bool) -> DFSDM1SELR {
        match value {
            false => DFSDM1SELR::RCC_PCLK2,
            true => DFSDM1SELR::SYS,
        }
    }
    #[doc = "Checks if the value of the field is `RCC_PCLK2`"]
    #[inline(always)]
    pub fn is_rcc_pclk2(&self) -> bool {
        *self == DFSDM1SELR::RCC_PCLK2
    }
    #[doc = "Checks if the value of the field is `SYS`"]
    #[inline(always)]
    pub fn is_sys(&self) -> bool {
        *self == DFSDM1SELR::SYS
    }
}
#[doc = "Values that can be written to the field `DFSDM1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DFSDM1SELW {
    #[doc = "rcc_pclk2 selected as peripheral clock"]
    RCC_PCLK2,
    #[doc = "System clock selected as peripheral clock"]
    SYS,
}
impl DFSDM1SELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _bits(&self) -> bool {
        match *self {
            DFSDM1SELW::RCC_PCLK2 => false,
            DFSDM1SELW::SYS => true,
        }
    }
}
#[doc = r"Proxy"]
pub struct _DFSDM1SELW<'a> {
    w: &'a mut W,
}
impl<'a> _DFSDM1SELW<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: DFSDM1SELW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "rcc_pclk2 selected as peripheral clock"]
    #[inline(always)]
    pub fn rcc_pclk2(self) -> &'a mut W {
        self.variant(DFSDM1SELW::RCC_PCLK2)
    }
    #[doc = "System clock selected as peripheral clock"]
    #[inline(always)]
    pub fn sys(self) -> &'a mut W {
        self.variant(DFSDM1SELW::SYS)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits &= !(0x01 << 24);
        self.w.bits |= ((value as u32) & 0x01) << 24;
        self.w
    }
}
#[doc = "Possible values of the field `FDCANSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FDCANSELR {
    #[doc = "HSE selected as peripheral clock"]
    HSE,
    #[doc = "pll1_q selected as peripheral clock"]
    PLL1_Q,
    #[doc = "pll2_q selected as peripheral clock"]
    PLL2_Q,
    #[doc = r"Reserved"]
    _Reserved(u8),
}
impl FDCANSELR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        match *self {
            FDCANSELR::HSE => 0,
            FDCANSELR::PLL1_Q => 0x01,
            FDCANSELR::PLL2_Q => 0x02,
            FDCANSELR::_Reserved(bits) => bits,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _from(value: u8) -> FDCANSELR {
        match value {
            0 => FDCANSELR::HSE,
            1 => FDCANSELR::PLL1_Q,
            2 => FDCANSELR::PLL2_Q,
            i => FDCANSELR::_Reserved(i),
        }
    }
    #[doc = "Checks if the value of the field is `HSE`"]
    #[inline(always)]
    pub fn is_hse(&self) -> bool {
        *self == FDCANSELR::HSE
    }
    #[doc = "Checks if the value of the field is `PLL1_Q`"]
    #[inline(always)]
    pub fn is_pll1_q(&self) -> bool {
        *self == FDCANSELR::PLL1_Q
    }
    #[doc = "Checks if the value of the field is `PLL2_Q`"]
    #[inline(always)]
    pub fn is_pll2_q(&self) -> bool {
        *self == FDCANSELR::PLL2_Q
    }
}
#[doc = "Values that can be written to the field `FDCANSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FDCANSELW {
    #[doc = "HSE selected as peripheral clock"]
    HSE,
    #[doc = "pll1_q selected as peripheral clock"]
    PLL1_Q,
    #[doc = "pll2_q selected as peripheral clock"]
    PLL2_Q,
}
impl FDCANSELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _bits(&self) -> u8 {
        match *self {
            FDCANSELW::HSE => 0,
            FDCANSELW::PLL1_Q => 1,
            FDCANSELW::PLL2_Q => 2,
        }
    }
}
#[doc = r"Proxy"]
pub struct _FDCANSELW<'a> {
    w: &'a mut W,
}
impl<'a> _FDCANSELW<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: FDCANSELW) -> &'a mut W {
        unsafe { self.bits(variant._bits()) }
    }
    #[doc = "HSE selected as peripheral clock"]
    #[inline(always)]
    pub fn hse(self) -> &'a mut W {
        self.variant(FDCANSELW::HSE)
    }
    #[doc = "pll1_q selected as peripheral clock"]
    #[inline(always)]
    pub fn pll1_q(self) -> &'a mut W {
        self.variant(FDCANSELW::PLL1_Q)
    }
    #[doc = "pll2_q selected as peripheral clock"]
    #[inline(always)]
    pub fn pll2_q(self) -> &'a mut W {
        self.variant(FDCANSELW::PLL2_Q)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x03 << 28);
        self.w.bits |= ((value as u32) & 0x03) << 28;
        self.w
    }
}
#[doc = "Possible values of the field `SWPSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SWPSELR {
    #[doc = "pclk selected as peripheral clock"]
    PCLK,
    #[doc = "hsi_ker selected as peripheral clock"]
    HSI_KER,
}
impl SWPSELR {
    #[doc = r"Returns `true` if the bit is clear (0)"]
    #[inline(always)]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r"Returns `true` if the bit is set (1)"]
    #[inline(always)]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bit(&self) -> bool {
        match *self {
            SWPSELR::PCLK => false,
            SWPSELR::HSI_KER => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _from(value: bool) -> SWPSELR {
        match value {
            false => SWPSELR::PCLK,
            true => SWPSELR::HSI_KER,
        }
    }
    #[doc = "Checks if the value of the field is `PCLK`"]
    #[inline(always)]
    pub fn is_pclk(&self) -> bool {
        *self == SWPSELR::PCLK
    }
    #[doc = "Checks if the value of the field is `HSI_KER`"]
    #[inline(always)]
    pub fn is_hsi_ker(&self) -> bool {
        *self == SWPSELR::HSI_KER
    }
}
#[doc = "Values that can be written to the field `SWPSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SWPSELW {
    #[doc = "pclk selected as peripheral clock"]
    PCLK,
    #[doc = "hsi_ker selected as peripheral clock"]
    HSI_KER,
}
impl SWPSELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _bits(&self) -> bool {
        match *self {
            SWPSELW::PCLK => false,
            SWPSELW::HSI_KER => true,
        }
    }
}
#[doc = r"Proxy"]
pub struct _SWPSELW<'a> {
    w: &'a mut W,
}
impl<'a> _SWPSELW<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SWPSELW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "pclk selected as peripheral clock"]
    #[inline(always)]
    pub fn pclk(self) -> &'a mut W {
        self.variant(SWPSELW::PCLK)
    }
    #[doc = "hsi_ker selected as peripheral clock"]
    #[inline(always)]
    pub fn hsi_ker(self) -> &'a mut W {
        self.variant(SWPSELW::HSI_KER)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits &= !(0x01 << 31);
        self.w.bits |= ((value as u32) & 0x01) << 31;
        self.w
    }
}
impl R {
    #[doc = r"Value of the register as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 0:2 - SAI1 and DFSDM1 kernel Aclk clock source selection"]
    #[inline(always)]
    pub fn sai1sel(&self) -> SAI1SELR {
        SAI1SELR::_from(((self.bits >> 0) & 0x07) as u8)
    }
    #[doc = "Bits 6:8 - SAI2 and SAI3 kernel clock source selection"]
    #[inline(always)]
    pub fn sai23sel(&self) -> SAI23SELR {
        SAI23SELR::_from(((self.bits >> 6) & 0x07) as u8)
    }
    #[doc = "Bits 12:14 - SPI/I2S1,2 and 3 kernel clock source selection"]
    #[inline(always)]
    pub fn spi123sel(&self) -> SPI123SELR {
        SPI123SELR::_from(((self.bits >> 12) & 0x07) as u8)
    }
    #[doc = "Bits 16:18 - SPI4 and 5 kernel clock source selection"]
    #[inline(always)]
    pub fn spi45sel(&self) -> SPI45SELR {
        SPI45SELR::_from(((self.bits >> 16) & 0x07) as u8)
    }
    #[doc = "Bits 20:21 - SPDIFRX kernel clock source selection"]
    #[inline(always)]
    pub fn spdifsel(&self) -> SPDIFSELR {
        SPDIFSELR::_from(((self.bits >> 20) & 0x03) as u8)
    }
    #[doc = "Bit 24 - DFSDM1 kernel Clk clock source selection"]
    #[inline(always)]
    pub fn dfsdm1sel(&self) -> DFSDM1SELR {
        DFSDM1SELR::_from(((self.bits >> 24) & 0x01) != 0)
    }
    #[doc = "Bits 28:29 - FDCAN kernel clock source selection"]
    #[inline(always)]
    pub fn fdcansel(&self) -> FDCANSELR {
        FDCANSELR::_from(((self.bits >> 28) & 0x03) as u8)
    }
    #[doc = "Bit 31 - SWPMI kernel clock source selection"]
    #[inline(always)]
    pub fn swpsel(&self) -> SWPSELR {
        SWPSELR::_from(((self.bits >> 31) & 0x01) != 0)
    }
}
impl W {
    #[doc = r"Writes raw bits to the register"]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
    #[doc = "Bits 0:2 - SAI1 and DFSDM1 kernel Aclk clock source selection"]
    #[inline(always)]
    pub fn sai1sel(&mut self) -> _SAI1SELW {
        _SAI1SELW { w: self }
    }
    #[doc = "Bits 6:8 - SAI2 and SAI3 kernel clock source selection"]
    #[inline(always)]
    pub fn sai23sel(&mut self) -> _SAI23SELW {
        _SAI23SELW { w: self }
    }
    #[doc = "Bits 12:14 - SPI/I2S1,2 and 3 kernel clock source selection"]
    #[inline(always)]
    pub fn spi123sel(&mut self) -> _SPI123SELW {
        _SPI123SELW { w: self }
    }
    #[doc = "Bits 16:18 - SPI4 and 5 kernel clock source selection"]
    #[inline(always)]
    pub fn spi45sel(&mut self) -> _SPI45SELW {
        _SPI45SELW { w: self }
    }
    #[doc = "Bits 20:21 - SPDIFRX kernel clock source selection"]
    #[inline(always)]
    pub fn spdifsel(&mut self) -> _SPDIFSELW {
        _SPDIFSELW { w: self }
    }
    #[doc = "Bit 24 - DFSDM1 kernel Clk clock source selection"]
    #[inline(always)]
    pub fn dfsdm1sel(&mut self) -> _DFSDM1SELW {
        _DFSDM1SELW { w: self }
    }
    #[doc = "Bits 28:29 - FDCAN kernel clock source selection"]
    #[inline(always)]
    pub fn fdcansel(&mut self) -> _FDCANSELW {
        _FDCANSELW { w: self }
    }
    #[doc = "Bit 31 - SWPMI kernel clock source selection"]
    #[inline(always)]
    pub fn swpsel(&mut self) -> _SWPSELW {
        _SWPSELW { w: self }
    }
}