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#[doc = r"Value read from the register"] pub struct R { bits: u32, } impl super::MMC_RX_INTERRUPT { #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } } #[doc = r"Value of the field"] pub struct RXCRCERPISR { bits: bool, } impl RXCRCERPISR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Value of the field"] pub struct RXALGNERPISR { bits: bool, } impl RXALGNERPISR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Value of the field"] pub struct RXUCGPISR { bits: bool, } impl RXUCGPISR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Value of the field"] pub struct RXLPIUSCISR { bits: bool, } impl RXLPIUSCISR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Value of the field"] pub struct RXLPITRCISR { bits: bool, } impl RXLPITRCISR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bit 5 - MMC Receive CRC Error Packet Counter Interrupt Status"] #[inline(always)] pub fn rxcrcerpis(&self) -> RXCRCERPISR { let bits = ((self.bits >> 5) & 0x01) != 0; RXCRCERPISR { bits } } #[doc = "Bit 6 - MMC Receive Alignment Error Packet Counter Interrupt Status"] #[inline(always)] pub fn rxalgnerpis(&self) -> RXALGNERPISR { let bits = ((self.bits >> 6) & 0x01) != 0; RXALGNERPISR { bits } } #[doc = "Bit 17 - MMC Receive Unicast Good Packet Counter Interrupt Status"] #[inline(always)] pub fn rxucgpis(&self) -> RXUCGPISR { let bits = ((self.bits >> 17) & 0x01) != 0; RXUCGPISR { bits } } #[doc = "Bit 26 - MMC Receive LPI microsecond counter interrupt status"] #[inline(always)] pub fn rxlpiuscis(&self) -> RXLPIUSCISR { let bits = ((self.bits >> 26) & 0x01) != 0; RXLPIUSCISR { bits } } #[doc = "Bit 27 - MMC Receive LPI transition counter interrupt status"] #[inline(always)] pub fn rxlpitrcis(&self) -> RXLPITRCISR { let bits = ((self.bits >> 27) & 0x01) != 0; RXLPITRCISR { bits } } }