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#[doc = r"Value read from the register"] pub struct R { bits: u32, } impl super::MIS { #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } } #[doc = r"Value of the field"] pub struct LINE_MISR { bits: bool, } impl LINE_MISR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Value of the field"] pub struct VSYNC_MISR { bits: bool, } impl VSYNC_MISR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Value of the field"] pub struct ERR_MISR { bits: bool, } impl ERR_MISR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Value of the field"] pub struct OVR_MISR { bits: bool, } impl OVR_MISR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Value of the field"] pub struct FRAME_MISR { bits: bool, } impl FRAME_MISR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bit 4 - Line masked interrupt status"] #[inline(always)] pub fn line_mis(&self) -> LINE_MISR { let bits = ((self.bits >> 4) & 0x01) != 0; LINE_MISR { bits } } #[doc = "Bit 3 - VSYNC masked interrupt status"] #[inline(always)] pub fn vsync_mis(&self) -> VSYNC_MISR { let bits = ((self.bits >> 3) & 0x01) != 0; VSYNC_MISR { bits } } #[doc = "Bit 2 - Synchronization error masked interrupt status"] #[inline(always)] pub fn err_mis(&self) -> ERR_MISR { let bits = ((self.bits >> 2) & 0x01) != 0; ERR_MISR { bits } } #[doc = "Bit 1 - Overrun masked interrupt status"] #[inline(always)] pub fn ovr_mis(&self) -> OVR_MISR { let bits = ((self.bits >> 1) & 0x01) != 0; OVR_MISR { bits } } #[doc = "Bit 0 - Capture complete masked interrupt status"] #[inline(always)] pub fn frame_mis(&self) -> FRAME_MISR { let bits = ((self.bits >> 0) & 0x01) != 0; FRAME_MISR { bits } } }