#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PLLCFGR {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0x01ff_0000
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `PLL1FRACEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLL1FRACENR {
#[doc = "Reset latch to tranfer FRACN to the Sigma-Delta modulator"]
RESET,
#[doc = "Set latch to tranfer FRACN to the Sigma-Delta modulator"]
SET,
}
impl PLL1FRACENR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
PLL1FRACENR::RESET => false,
PLL1FRACENR::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> PLL1FRACENR {
match value {
false => PLL1FRACENR::RESET,
true => PLL1FRACENR::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline(always)]
pub fn is_reset(&self) -> bool {
*self == PLL1FRACENR::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline(always)]
pub fn is_set(&self) -> bool {
*self == PLL1FRACENR::SET
}
}
#[doc = "Values that can be written to the field `PLL1FRACEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLL1FRACENW {
#[doc = "Reset latch to tranfer FRACN to the Sigma-Delta modulator"]
RESET,
#[doc = "Set latch to tranfer FRACN to the Sigma-Delta modulator"]
SET,
}
impl PLL1FRACENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
PLL1FRACENW::RESET => false,
PLL1FRACENW::SET => true,
}
}
}
#[doc = r"Proxy"]
pub struct _PLL1FRACENW<'a> {
w: &'a mut W,
}
impl<'a> _PLL1FRACENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PLL1FRACENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Reset latch to tranfer FRACN to the Sigma-Delta modulator"]
#[inline(always)]
pub fn reset(self) -> &'a mut W {
self.variant(PLL1FRACENW::RESET)
}
#[doc = "Set latch to tranfer FRACN to the Sigma-Delta modulator"]
#[inline(always)]
pub fn set(self) -> &'a mut W {
self.variant(PLL1FRACENW::SET)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 0);
self.w.bits |= ((value as u32) & 0x01) << 0;
self.w
}
}
#[doc = "Possible values of the field `PLL1VCOSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLL1VCOSELR {
#[doc = "VCO frequency range 192 to 836 MHz"]
WIDEVCO,
#[doc = "VCO frequency range 150 to 420 MHz"]
MEDIUMVCO,
}
impl PLL1VCOSELR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
PLL1VCOSELR::WIDEVCO => false,
PLL1VCOSELR::MEDIUMVCO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> PLL1VCOSELR {
match value {
false => PLL1VCOSELR::WIDEVCO,
true => PLL1VCOSELR::MEDIUMVCO,
}
}
#[doc = "Checks if the value of the field is `WIDEVCO`"]
#[inline(always)]
pub fn is_wide_vco(&self) -> bool {
*self == PLL1VCOSELR::WIDEVCO
}
#[doc = "Checks if the value of the field is `MEDIUMVCO`"]
#[inline(always)]
pub fn is_medium_vco(&self) -> bool {
*self == PLL1VCOSELR::MEDIUMVCO
}
}
#[doc = "Values that can be written to the field `PLL1VCOSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLL1VCOSELW {
#[doc = "VCO frequency range 192 to 836 MHz"]
WIDEVCO,
#[doc = "VCO frequency range 150 to 420 MHz"]
MEDIUMVCO,
}
impl PLL1VCOSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
PLL1VCOSELW::WIDEVCO => false,
PLL1VCOSELW::MEDIUMVCO => true,
}
}
}
#[doc = r"Proxy"]
pub struct _PLL1VCOSELW<'a> {
w: &'a mut W,
}
impl<'a> _PLL1VCOSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PLL1VCOSELW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "VCO frequency range 192 to 836 MHz"]
#[inline(always)]
pub fn wide_vco(self) -> &'a mut W {
self.variant(PLL1VCOSELW::WIDEVCO)
}
#[doc = "VCO frequency range 150 to 420 MHz"]
#[inline(always)]
pub fn medium_vco(self) -> &'a mut W {
self.variant(PLL1VCOSELW::MEDIUMVCO)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 1);
self.w.bits |= ((value as u32) & 0x01) << 1;
self.w
}
}
#[doc = "Possible values of the field `PLL1RGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLL1RGER {
#[doc = "Frequency is between 1 and 2 MHz"]
RANGE1,
#[doc = "Frequency is between 2 and 4 MHz"]
RANGE2,
#[doc = "Frequency is between 4 and 8 MHz"]
RANGE4,
#[doc = "Frequency is between 8 and 16 MHz"]
RANGE8,
}
impl PLL1RGER {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
PLL1RGER::RANGE1 => 0,
PLL1RGER::RANGE2 => 0x01,
PLL1RGER::RANGE4 => 0x02,
PLL1RGER::RANGE8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> PLL1RGER {
match value {
0 => PLL1RGER::RANGE1,
1 => PLL1RGER::RANGE2,
2 => PLL1RGER::RANGE4,
3 => PLL1RGER::RANGE8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `RANGE1`"]
#[inline(always)]
pub fn is_range1(&self) -> bool {
*self == PLL1RGER::RANGE1
}
#[doc = "Checks if the value of the field is `RANGE2`"]
#[inline(always)]
pub fn is_range2(&self) -> bool {
*self == PLL1RGER::RANGE2
}
#[doc = "Checks if the value of the field is `RANGE4`"]
#[inline(always)]
pub fn is_range4(&self) -> bool {
*self == PLL1RGER::RANGE4
}
#[doc = "Checks if the value of the field is `RANGE8`"]
#[inline(always)]
pub fn is_range8(&self) -> bool {
*self == PLL1RGER::RANGE8
}
}
#[doc = "Values that can be written to the field `PLL1RGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLL1RGEW {
#[doc = "Frequency is between 1 and 2 MHz"]
RANGE1,
#[doc = "Frequency is between 2 and 4 MHz"]
RANGE2,
#[doc = "Frequency is between 4 and 8 MHz"]
RANGE4,
#[doc = "Frequency is between 8 and 16 MHz"]
RANGE8,
}
impl PLL1RGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
PLL1RGEW::RANGE1 => 0,
PLL1RGEW::RANGE2 => 1,
PLL1RGEW::RANGE4 => 2,
PLL1RGEW::RANGE8 => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _PLL1RGEW<'a> {
w: &'a mut W,
}
impl<'a> _PLL1RGEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PLL1RGEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Frequency is between 1 and 2 MHz"]
#[inline(always)]
pub fn range1(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE1)
}
#[doc = "Frequency is between 2 and 4 MHz"]
#[inline(always)]
pub fn range2(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE2)
}
#[doc = "Frequency is between 4 and 8 MHz"]
#[inline(always)]
pub fn range4(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE4)
}
#[doc = "Frequency is between 8 and 16 MHz"]
#[inline(always)]
pub fn range8(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE8)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 2);
self.w.bits |= ((value as u32) & 0x03) << 2;
self.w
}
}
#[doc = "Possible values of the field `PLL2FRACEN`"]
pub type PLL2FRACENR = PLL1FRACENR;
#[doc = "Values that can be written to the field `PLL2FRACEN`"]
pub type PLL2FRACENW = PLL1FRACENW;
#[doc = r"Proxy"]
pub struct _PLL2FRACENW<'a> {
w: &'a mut W,
}
impl<'a> _PLL2FRACENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PLL2FRACENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Reset latch to tranfer FRACN to the Sigma-Delta modulator"]
#[inline(always)]
pub fn reset(self) -> &'a mut W {
self.variant(PLL1FRACENW::RESET)
}
#[doc = "Set latch to tranfer FRACN to the Sigma-Delta modulator"]
#[inline(always)]
pub fn set(self) -> &'a mut W {
self.variant(PLL1FRACENW::SET)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 4);
self.w.bits |= ((value as u32) & 0x01) << 4;
self.w
}
}
#[doc = "Possible values of the field `PLL2VCOSEL`"]
pub type PLL2VCOSELR = PLL1VCOSELR;
#[doc = "Values that can be written to the field `PLL2VCOSEL`"]
pub type PLL2VCOSELW = PLL1VCOSELW;
#[doc = r"Proxy"]
pub struct _PLL2VCOSELW<'a> {
w: &'a mut W,
}
impl<'a> _PLL2VCOSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PLL2VCOSELW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "VCO frequency range 192 to 836 MHz"]
#[inline(always)]
pub fn wide_vco(self) -> &'a mut W {
self.variant(PLL1VCOSELW::WIDEVCO)
}
#[doc = "VCO frequency range 150 to 420 MHz"]
#[inline(always)]
pub fn medium_vco(self) -> &'a mut W {
self.variant(PLL1VCOSELW::MEDIUMVCO)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 5);
self.w.bits |= ((value as u32) & 0x01) << 5;
self.w
}
}
#[doc = "Possible values of the field `PLL2RGE`"]
pub type PLL2RGER = PLL1RGER;
#[doc = "Values that can be written to the field `PLL2RGE`"]
pub type PLL2RGEW = PLL1RGEW;
#[doc = r"Proxy"]
pub struct _PLL2RGEW<'a> {
w: &'a mut W,
}
impl<'a> _PLL2RGEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PLL2RGEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Frequency is between 1 and 2 MHz"]
#[inline(always)]
pub fn range1(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE1)
}
#[doc = "Frequency is between 2 and 4 MHz"]
#[inline(always)]
pub fn range2(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE2)
}
#[doc = "Frequency is between 4 and 8 MHz"]
#[inline(always)]
pub fn range4(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE4)
}
#[doc = "Frequency is between 8 and 16 MHz"]
#[inline(always)]
pub fn range8(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE8)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 6);
self.w.bits |= ((value as u32) & 0x03) << 6;
self.w
}
}
#[doc = "Possible values of the field `PLL3FRACEN`"]
pub type PLL3FRACENR = PLL1FRACENR;
#[doc = "Values that can be written to the field `PLL3FRACEN`"]
pub type PLL3FRACENW = PLL1FRACENW;
#[doc = r"Proxy"]
pub struct _PLL3FRACENW<'a> {
w: &'a mut W,
}
impl<'a> _PLL3FRACENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PLL3FRACENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Reset latch to tranfer FRACN to the Sigma-Delta modulator"]
#[inline(always)]
pub fn reset(self) -> &'a mut W {
self.variant(PLL1FRACENW::RESET)
}
#[doc = "Set latch to tranfer FRACN to the Sigma-Delta modulator"]
#[inline(always)]
pub fn set(self) -> &'a mut W {
self.variant(PLL1FRACENW::SET)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 8);
self.w.bits |= ((value as u32) & 0x01) << 8;
self.w
}
}
#[doc = "Possible values of the field `PLL3VCOSEL`"]
pub type PLL3VCOSELR = PLL1VCOSELR;
#[doc = "Values that can be written to the field `PLL3VCOSEL`"]
pub type PLL3VCOSELW = PLL1VCOSELW;
#[doc = r"Proxy"]
pub struct _PLL3VCOSELW<'a> {
w: &'a mut W,
}
impl<'a> _PLL3VCOSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PLL3VCOSELW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "VCO frequency range 192 to 836 MHz"]
#[inline(always)]
pub fn wide_vco(self) -> &'a mut W {
self.variant(PLL1VCOSELW::WIDEVCO)
}
#[doc = "VCO frequency range 150 to 420 MHz"]
#[inline(always)]
pub fn medium_vco(self) -> &'a mut W {
self.variant(PLL1VCOSELW::MEDIUMVCO)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 9);
self.w.bits |= ((value as u32) & 0x01) << 9;
self.w
}
}
#[doc = "Possible values of the field `PLL3RGE`"]
pub type PLL3RGER = PLL1RGER;
#[doc = "Values that can be written to the field `PLL3RGE`"]
pub type PLL3RGEW = PLL1RGEW;
#[doc = r"Proxy"]
pub struct _PLL3RGEW<'a> {
w: &'a mut W,
}
impl<'a> _PLL3RGEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PLL3RGEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Frequency is between 1 and 2 MHz"]
#[inline(always)]
pub fn range1(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE1)
}
#[doc = "Frequency is between 2 and 4 MHz"]
#[inline(always)]
pub fn range2(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE2)
}
#[doc = "Frequency is between 4 and 8 MHz"]
#[inline(always)]
pub fn range4(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE4)
}
#[doc = "Frequency is between 8 and 16 MHz"]
#[inline(always)]
pub fn range8(self) -> &'a mut W {
self.variant(PLL1RGEW::RANGE8)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 10);
self.w.bits |= ((value as u32) & 0x03) << 10;
self.w
}
}
#[doc = "Possible values of the field `DIVP1EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVP1ENR {
#[doc = "Clock ouput is disabled"]
DISABLED,
#[doc = "Clock output is enabled"]
ENABLED,
}
impl DIVP1ENR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
DIVP1ENR::DISABLED => false,
DIVP1ENR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> DIVP1ENR {
match value {
false => DIVP1ENR::DISABLED,
true => DIVP1ENR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == DIVP1ENR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == DIVP1ENR::ENABLED
}
}
#[doc = "Values that can be written to the field `DIVP1EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVP1ENW {
#[doc = "Clock ouput is disabled"]
DISABLED,
#[doc = "Clock output is enabled"]
ENABLED,
}
impl DIVP1ENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
DIVP1ENW::DISABLED => false,
DIVP1ENW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _DIVP1ENW<'a> {
w: &'a mut W,
}
impl<'a> _DIVP1ENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIVP1ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock ouput is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DIVP1ENW::DISABLED)
}
#[doc = "Clock output is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DIVP1ENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 16);
self.w.bits |= ((value as u32) & 0x01) << 16;
self.w
}
}
#[doc = "Possible values of the field `DIVQ1EN`"]
pub type DIVQ1ENR = DIVP1ENR;
#[doc = "Values that can be written to the field `DIVQ1EN`"]
pub type DIVQ1ENW = DIVP1ENW;
#[doc = r"Proxy"]
pub struct _DIVQ1ENW<'a> {
w: &'a mut W,
}
impl<'a> _DIVQ1ENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIVQ1ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock ouput is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DIVP1ENW::DISABLED)
}
#[doc = "Clock output is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DIVP1ENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 17);
self.w.bits |= ((value as u32) & 0x01) << 17;
self.w
}
}
#[doc = "Possible values of the field `DIVR1EN`"]
pub type DIVR1ENR = DIVP1ENR;
#[doc = "Values that can be written to the field `DIVR1EN`"]
pub type DIVR1ENW = DIVP1ENW;
#[doc = r"Proxy"]
pub struct _DIVR1ENW<'a> {
w: &'a mut W,
}
impl<'a> _DIVR1ENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIVR1ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock ouput is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DIVP1ENW::DISABLED)
}
#[doc = "Clock output is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DIVP1ENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 18);
self.w.bits |= ((value as u32) & 0x01) << 18;
self.w
}
}
#[doc = "Possible values of the field `DIVP2EN`"]
pub type DIVP2ENR = DIVP1ENR;
#[doc = "Values that can be written to the field `DIVP2EN`"]
pub type DIVP2ENW = DIVP1ENW;
#[doc = r"Proxy"]
pub struct _DIVP2ENW<'a> {
w: &'a mut W,
}
impl<'a> _DIVP2ENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIVP2ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock ouput is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DIVP1ENW::DISABLED)
}
#[doc = "Clock output is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DIVP1ENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 19);
self.w.bits |= ((value as u32) & 0x01) << 19;
self.w
}
}
#[doc = "Possible values of the field `DIVQ2EN`"]
pub type DIVQ2ENR = DIVP1ENR;
#[doc = "Values that can be written to the field `DIVQ2EN`"]
pub type DIVQ2ENW = DIVP1ENW;
#[doc = r"Proxy"]
pub struct _DIVQ2ENW<'a> {
w: &'a mut W,
}
impl<'a> _DIVQ2ENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIVQ2ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock ouput is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DIVP1ENW::DISABLED)
}
#[doc = "Clock output is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DIVP1ENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 20);
self.w.bits |= ((value as u32) & 0x01) << 20;
self.w
}
}
#[doc = "Possible values of the field `DIVR2EN`"]
pub type DIVR2ENR = DIVP1ENR;
#[doc = "Values that can be written to the field `DIVR2EN`"]
pub type DIVR2ENW = DIVP1ENW;
#[doc = r"Proxy"]
pub struct _DIVR2ENW<'a> {
w: &'a mut W,
}
impl<'a> _DIVR2ENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIVR2ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock ouput is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DIVP1ENW::DISABLED)
}
#[doc = "Clock output is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DIVP1ENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 21);
self.w.bits |= ((value as u32) & 0x01) << 21;
self.w
}
}
#[doc = "Possible values of the field `DIVP3EN`"]
pub type DIVP3ENR = DIVP1ENR;
#[doc = "Values that can be written to the field `DIVP3EN`"]
pub type DIVP3ENW = DIVP1ENW;
#[doc = r"Proxy"]
pub struct _DIVP3ENW<'a> {
w: &'a mut W,
}
impl<'a> _DIVP3ENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIVP3ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock ouput is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DIVP1ENW::DISABLED)
}
#[doc = "Clock output is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DIVP1ENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 22);
self.w.bits |= ((value as u32) & 0x01) << 22;
self.w
}
}
#[doc = "Possible values of the field `DIVQ3EN`"]
pub type DIVQ3ENR = DIVP1ENR;
#[doc = "Values that can be written to the field `DIVQ3EN`"]
pub type DIVQ3ENW = DIVP1ENW;
#[doc = r"Proxy"]
pub struct _DIVQ3ENW<'a> {
w: &'a mut W,
}
impl<'a> _DIVQ3ENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIVQ3ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock ouput is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DIVP1ENW::DISABLED)
}
#[doc = "Clock output is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DIVP1ENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 23);
self.w.bits |= ((value as u32) & 0x01) << 23;
self.w
}
}
#[doc = "Possible values of the field `DIVR3EN`"]
pub type DIVR3ENR = DIVP1ENR;
#[doc = "Values that can be written to the field `DIVR3EN`"]
pub type DIVR3ENW = DIVP1ENW;
#[doc = r"Proxy"]
pub struct _DIVR3ENW<'a> {
w: &'a mut W,
}
impl<'a> _DIVR3ENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIVR3ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock ouput is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DIVP1ENW::DISABLED)
}
#[doc = "Clock output is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DIVP1ENW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 24);
self.w.bits |= ((value as u32) & 0x01) << 24;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - PLL1 fractional latch enable"]
#[inline(always)]
pub fn pll1fracen(&self) -> PLL1FRACENR {
PLL1FRACENR::_from(((self.bits >> 0) & 0x01) != 0)
}
#[doc = "Bit 1 - PLL1 VCO selection"]
#[inline(always)]
pub fn pll1vcosel(&self) -> PLL1VCOSELR {
PLL1VCOSELR::_from(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bits 2:3 - PLL1 input frequency range"]
#[inline(always)]
pub fn pll1rge(&self) -> PLL1RGER {
PLL1RGER::_from(((self.bits >> 2) & 0x03) as u8)
}
#[doc = "Bit 4 - PLL2 fractional latch enable"]
#[inline(always)]
pub fn pll2fracen(&self) -> PLL2FRACENR {
PLL2FRACENR::_from(((self.bits >> 4) & 0x01) != 0)
}
#[doc = "Bit 5 - PLL2 VCO selection"]
#[inline(always)]
pub fn pll2vcosel(&self) -> PLL2VCOSELR {
PLL2VCOSELR::_from(((self.bits >> 5) & 0x01) != 0)
}
#[doc = "Bits 6:7 - PLL2 input frequency range"]
#[inline(always)]
pub fn pll2rge(&self) -> PLL2RGER {
PLL2RGER::_from(((self.bits >> 6) & 0x03) as u8)
}
#[doc = "Bit 8 - PLL3 fractional latch enable"]
#[inline(always)]
pub fn pll3fracen(&self) -> PLL3FRACENR {
PLL3FRACENR::_from(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 9 - PLL3 VCO selection"]
#[inline(always)]
pub fn pll3vcosel(&self) -> PLL3VCOSELR {
PLL3VCOSELR::_from(((self.bits >> 9) & 0x01) != 0)
}
#[doc = "Bits 10:11 - PLL3 input frequency range"]
#[inline(always)]
pub fn pll3rge(&self) -> PLL3RGER {
PLL3RGER::_from(((self.bits >> 10) & 0x03) as u8)
}
#[doc = "Bit 16 - PLL1 DIVP divider output enable"]
#[inline(always)]
pub fn divp1en(&self) -> DIVP1ENR {
DIVP1ENR::_from(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bit 17 - PLL1 DIVQ divider output enable"]
#[inline(always)]
pub fn divq1en(&self) -> DIVQ1ENR {
DIVQ1ENR::_from(((self.bits >> 17) & 0x01) != 0)
}
#[doc = "Bit 18 - PLL1 DIVR divider output enable"]
#[inline(always)]
pub fn divr1en(&self) -> DIVR1ENR {
DIVR1ENR::_from(((self.bits >> 18) & 0x01) != 0)
}
#[doc = "Bit 19 - PLL2 DIVP divider output enable"]
#[inline(always)]
pub fn divp2en(&self) -> DIVP2ENR {
DIVP2ENR::_from(((self.bits >> 19) & 0x01) != 0)
}
#[doc = "Bit 20 - PLL2 DIVQ divider output enable"]
#[inline(always)]
pub fn divq2en(&self) -> DIVQ2ENR {
DIVQ2ENR::_from(((self.bits >> 20) & 0x01) != 0)
}
#[doc = "Bit 21 - PLL2 DIVR divider output enable"]
#[inline(always)]
pub fn divr2en(&self) -> DIVR2ENR {
DIVR2ENR::_from(((self.bits >> 21) & 0x01) != 0)
}
#[doc = "Bit 22 - PLL3 DIVP divider output enable"]
#[inline(always)]
pub fn divp3en(&self) -> DIVP3ENR {
DIVP3ENR::_from(((self.bits >> 22) & 0x01) != 0)
}
#[doc = "Bit 23 - PLL3 DIVQ divider output enable"]
#[inline(always)]
pub fn divq3en(&self) -> DIVQ3ENR {
DIVQ3ENR::_from(((self.bits >> 23) & 0x01) != 0)
}
#[doc = "Bit 24 - PLL3 DIVR divider output enable"]
#[inline(always)]
pub fn divr3en(&self) -> DIVR3ENR {
DIVR3ENR::_from(((self.bits >> 24) & 0x01) != 0)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - PLL1 fractional latch enable"]
#[inline(always)]
pub fn pll1fracen(&mut self) -> _PLL1FRACENW {
_PLL1FRACENW { w: self }
}
#[doc = "Bit 1 - PLL1 VCO selection"]
#[inline(always)]
pub fn pll1vcosel(&mut self) -> _PLL1VCOSELW {
_PLL1VCOSELW { w: self }
}
#[doc = "Bits 2:3 - PLL1 input frequency range"]
#[inline(always)]
pub fn pll1rge(&mut self) -> _PLL1RGEW {
_PLL1RGEW { w: self }
}
#[doc = "Bit 4 - PLL2 fractional latch enable"]
#[inline(always)]
pub fn pll2fracen(&mut self) -> _PLL2FRACENW {
_PLL2FRACENW { w: self }
}
#[doc = "Bit 5 - PLL2 VCO selection"]
#[inline(always)]
pub fn pll2vcosel(&mut self) -> _PLL2VCOSELW {
_PLL2VCOSELW { w: self }
}
#[doc = "Bits 6:7 - PLL2 input frequency range"]
#[inline(always)]
pub fn pll2rge(&mut self) -> _PLL2RGEW {
_PLL2RGEW { w: self }
}
#[doc = "Bit 8 - PLL3 fractional latch enable"]
#[inline(always)]
pub fn pll3fracen(&mut self) -> _PLL3FRACENW {
_PLL3FRACENW { w: self }
}
#[doc = "Bit 9 - PLL3 VCO selection"]
#[inline(always)]
pub fn pll3vcosel(&mut self) -> _PLL3VCOSELW {
_PLL3VCOSELW { w: self }
}
#[doc = "Bits 10:11 - PLL3 input frequency range"]
#[inline(always)]
pub fn pll3rge(&mut self) -> _PLL3RGEW {
_PLL3RGEW { w: self }
}
#[doc = "Bit 16 - PLL1 DIVP divider output enable"]
#[inline(always)]
pub fn divp1en(&mut self) -> _DIVP1ENW {
_DIVP1ENW { w: self }
}
#[doc = "Bit 17 - PLL1 DIVQ divider output enable"]
#[inline(always)]
pub fn divq1en(&mut self) -> _DIVQ1ENW {
_DIVQ1ENW { w: self }
}
#[doc = "Bit 18 - PLL1 DIVR divider output enable"]
#[inline(always)]
pub fn divr1en(&mut self) -> _DIVR1ENW {
_DIVR1ENW { w: self }
}
#[doc = "Bit 19 - PLL2 DIVP divider output enable"]
#[inline(always)]
pub fn divp2en(&mut self) -> _DIVP2ENW {
_DIVP2ENW { w: self }
}
#[doc = "Bit 20 - PLL2 DIVQ divider output enable"]
#[inline(always)]
pub fn divq2en(&mut self) -> _DIVQ2ENW {
_DIVQ2ENW { w: self }
}
#[doc = "Bit 21 - PLL2 DIVR divider output enable"]
#[inline(always)]
pub fn divr2en(&mut self) -> _DIVR2ENW {
_DIVR2ENW { w: self }
}
#[doc = "Bit 22 - PLL3 DIVP divider output enable"]
#[inline(always)]
pub fn divp3en(&mut self) -> _DIVP3ENW {
_DIVP3ENW { w: self }
}
#[doc = "Bit 23 - PLL3 DIVQ divider output enable"]
#[inline(always)]
pub fn divq3en(&mut self) -> _DIVQ3ENW {
_DIVQ3ENW { w: self }
}
#[doc = "Bit 24 - PLL3 DIVR divider output enable"]
#[inline(always)]
pub fn divr3en(&mut self) -> _DIVR3ENW {
_DIVR3ENW { w: self }
}
}