#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFGR {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = r"Value of the field"]
pub struct JQDISR {
bits: bool,
}
impl JQDISR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _JQDISW<'a> {
w: &'a mut W,
}
impl<'a> _JQDISW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 31);
self.w.bits |= ((value as u32) & 0x01) << 31;
self.w
}
}
#[doc = r"Value of the field"]
pub struct AWDCH1CHR {
bits: u8,
}
impl AWDCH1CHR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _AWDCH1CHW<'a> {
w: &'a mut W,
}
impl<'a> _AWDCH1CHW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 26);
self.w.bits |= ((value as u32) & 0x1f) << 26;
self.w
}
}
#[doc = r"Value of the field"]
pub struct JAUTOR {
bits: bool,
}
impl JAUTOR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _JAUTOW<'a> {
w: &'a mut W,
}
impl<'a> _JAUTOW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 25);
self.w.bits |= ((value as u32) & 0x01) << 25;
self.w
}
}
#[doc = r"Value of the field"]
pub struct JAWD1ENR {
bits: bool,
}
impl JAWD1ENR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _JAWD1ENW<'a> {
w: &'a mut W,
}
impl<'a> _JAWD1ENW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 24);
self.w.bits |= ((value as u32) & 0x01) << 24;
self.w
}
}
#[doc = r"Value of the field"]
pub struct AWD1ENR {
bits: bool,
}
impl AWD1ENR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _AWD1ENW<'a> {
w: &'a mut W,
}
impl<'a> _AWD1ENW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 23);
self.w.bits |= ((value as u32) & 0x01) << 23;
self.w
}
}
#[doc = r"Value of the field"]
pub struct AWD1SGLR {
bits: bool,
}
impl AWD1SGLR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _AWD1SGLW<'a> {
w: &'a mut W,
}
impl<'a> _AWD1SGLW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 22);
self.w.bits |= ((value as u32) & 0x01) << 22;
self.w
}
}
#[doc = r"Value of the field"]
pub struct JQMR {
bits: bool,
}
impl JQMR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _JQMW<'a> {
w: &'a mut W,
}
impl<'a> _JQMW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 21);
self.w.bits |= ((value as u32) & 0x01) << 21;
self.w
}
}
#[doc = r"Value of the field"]
pub struct JDISCENR {
bits: bool,
}
impl JDISCENR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _JDISCENW<'a> {
w: &'a mut W,
}
impl<'a> _JDISCENW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 20);
self.w.bits |= ((value as u32) & 0x01) << 20;
self.w
}
}
#[doc = r"Value of the field"]
pub struct DISCNUMR {
bits: u8,
}
impl DISCNUMR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _DISCNUMW<'a> {
w: &'a mut W,
}
impl<'a> _DISCNUMW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 17);
self.w.bits |= ((value as u32) & 0x07) << 17;
self.w
}
}
#[doc = r"Value of the field"]
pub struct DISCENR {
bits: bool,
}
impl DISCENR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _DISCENW<'a> {
w: &'a mut W,
}
impl<'a> _DISCENW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 16);
self.w.bits |= ((value as u32) & 0x01) << 16;
self.w
}
}
#[doc = r"Value of the field"]
pub struct AUTDLYR {
bits: bool,
}
impl AUTDLYR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _AUTDLYW<'a> {
w: &'a mut W,
}
impl<'a> _AUTDLYW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 14);
self.w.bits |= ((value as u32) & 0x01) << 14;
self.w
}
}
#[doc = r"Value of the field"]
pub struct CONTR {
bits: bool,
}
impl CONTR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _CONTW<'a> {
w: &'a mut W,
}
impl<'a> _CONTW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 13);
self.w.bits |= ((value as u32) & 0x01) << 13;
self.w
}
}
#[doc = r"Value of the field"]
pub struct OVRMODR {
bits: bool,
}
impl OVRMODR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _OVRMODW<'a> {
w: &'a mut W,
}
impl<'a> _OVRMODW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 12);
self.w.bits |= ((value as u32) & 0x01) << 12;
self.w
}
}
#[doc = "Possible values of the field `EXTEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTENR {
#[doc = "Trigger detection disabled"]
DISABLED,
#[doc = "Trigger detection on the rising edge"]
RISINGEDGE,
#[doc = "Trigger detection on the falling edge"]
FALLINGEDGE,
#[doc = "Trigger detection on both the rising and falling edges"]
BOTHEDGES,
}
impl EXTENR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
EXTENR::DISABLED => 0,
EXTENR::RISINGEDGE => 0x01,
EXTENR::FALLINGEDGE => 0x02,
EXTENR::BOTHEDGES => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> EXTENR {
match value {
0 => EXTENR::DISABLED,
1 => EXTENR::RISINGEDGE,
2 => EXTENR::FALLINGEDGE,
3 => EXTENR::BOTHEDGES,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == EXTENR::DISABLED
}
#[doc = "Checks if the value of the field is `RISINGEDGE`"]
#[inline(always)]
pub fn is_rising_edge(&self) -> bool {
*self == EXTENR::RISINGEDGE
}
#[doc = "Checks if the value of the field is `FALLINGEDGE`"]
#[inline(always)]
pub fn is_falling_edge(&self) -> bool {
*self == EXTENR::FALLINGEDGE
}
#[doc = "Checks if the value of the field is `BOTHEDGES`"]
#[inline(always)]
pub fn is_both_edges(&self) -> bool {
*self == EXTENR::BOTHEDGES
}
}
#[doc = "Values that can be written to the field `EXTEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTENW {
#[doc = "Trigger detection disabled"]
DISABLED,
#[doc = "Trigger detection on the rising edge"]
RISINGEDGE,
#[doc = "Trigger detection on the falling edge"]
FALLINGEDGE,
#[doc = "Trigger detection on both the rising and falling edges"]
BOTHEDGES,
}
impl EXTENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
EXTENW::DISABLED => 0,
EXTENW::RISINGEDGE => 1,
EXTENW::FALLINGEDGE => 2,
EXTENW::BOTHEDGES => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _EXTENW<'a> {
w: &'a mut W,
}
impl<'a> _EXTENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: EXTENW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Trigger detection disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(EXTENW::DISABLED)
}
#[doc = "Trigger detection on the rising edge"]
#[inline(always)]
pub fn rising_edge(self) -> &'a mut W {
self.variant(EXTENW::RISINGEDGE)
}
#[doc = "Trigger detection on the falling edge"]
#[inline(always)]
pub fn falling_edge(self) -> &'a mut W {
self.variant(EXTENW::FALLINGEDGE)
}
#[doc = "Trigger detection on both the rising and falling edges"]
#[inline(always)]
pub fn both_edges(self) -> &'a mut W {
self.variant(EXTENW::BOTHEDGES)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 10);
self.w.bits |= ((value as u32) & 0x03) << 10;
self.w
}
}
#[doc = "Possible values of the field `EXTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTSELR {
#[doc = "Timer 1 CC1 event"]
TIM1_CC1,
#[doc = "Timer 1 CC2 event"]
TIM1_CC2,
#[doc = "Timer 1 CC3 event"]
TIM1_CC3,
#[doc = "Timer 2 CC2 event"]
TIM2_CC2,
#[doc = "Timer 3 TRGO event"]
TIM3_TRGO,
#[doc = "Timer 4 CC4 event"]
TIM4_CC4,
#[doc = "EXTI line 11"]
EXTI11,
#[doc = "Timer 8 TRGO event"]
TIM8_TRGO,
#[doc = "Timer 8 TRGO2 event"]
TIM8_TRGO2,
#[doc = "Timer 1 TRGO event"]
TIM1_TRGO,
#[doc = "Timer 1 TRGO2 event"]
TIM1_TRGO2,
#[doc = "Timer 2 TRGO event"]
TIM2_TRGO,
#[doc = "Timer 4 TRGO event"]
TIM4_TRGO,
#[doc = "Timer 6 TRGO event"]
TIM6_TRGO,
#[doc = "Timer 15 TRGO event"]
TIM15_TRGO,
#[doc = "Timer 3 CC4 event"]
TIM3_CC4,
#[doc = "HRTIM1_ADCTRG1 event"]
HRTIM1_ADCTRG1,
#[doc = "HRTIM1_ADCTRG3 event"]
HRTIM1_ADCTRG3,
#[doc = "LPTIM1_OUT event"]
LPTIM1_OUT,
#[doc = "LPTIM2_OUT event"]
LPTIM2_OUT,
#[doc = "LPTIM3_OUT event"]
LPTIM3_OUT,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl EXTSELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
EXTSELR::TIM1_CC1 => 0,
EXTSELR::TIM1_CC2 => 0x01,
EXTSELR::TIM1_CC3 => 0x02,
EXTSELR::TIM2_CC2 => 0x03,
EXTSELR::TIM3_TRGO => 0x04,
EXTSELR::TIM4_CC4 => 0x05,
EXTSELR::EXTI11 => 0x06,
EXTSELR::TIM8_TRGO => 0x07,
EXTSELR::TIM8_TRGO2 => 0x08,
EXTSELR::TIM1_TRGO => 0x09,
EXTSELR::TIM1_TRGO2 => 0x0a,
EXTSELR::TIM2_TRGO => 0x0b,
EXTSELR::TIM4_TRGO => 0x0c,
EXTSELR::TIM6_TRGO => 0x0d,
EXTSELR::TIM15_TRGO => 0x0e,
EXTSELR::TIM3_CC4 => 0x0f,
EXTSELR::HRTIM1_ADCTRG1 => 0x10,
EXTSELR::HRTIM1_ADCTRG3 => 0x11,
EXTSELR::LPTIM1_OUT => 0x12,
EXTSELR::LPTIM2_OUT => 0x13,
EXTSELR::LPTIM3_OUT => 0x14,
EXTSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> EXTSELR {
match value {
0 => EXTSELR::TIM1_CC1,
1 => EXTSELR::TIM1_CC2,
2 => EXTSELR::TIM1_CC3,
3 => EXTSELR::TIM2_CC2,
4 => EXTSELR::TIM3_TRGO,
5 => EXTSELR::TIM4_CC4,
6 => EXTSELR::EXTI11,
7 => EXTSELR::TIM8_TRGO,
8 => EXTSELR::TIM8_TRGO2,
9 => EXTSELR::TIM1_TRGO,
10 => EXTSELR::TIM1_TRGO2,
11 => EXTSELR::TIM2_TRGO,
12 => EXTSELR::TIM4_TRGO,
13 => EXTSELR::TIM6_TRGO,
14 => EXTSELR::TIM15_TRGO,
15 => EXTSELR::TIM3_CC4,
16 => EXTSELR::HRTIM1_ADCTRG1,
17 => EXTSELR::HRTIM1_ADCTRG3,
18 => EXTSELR::LPTIM1_OUT,
19 => EXTSELR::LPTIM2_OUT,
20 => EXTSELR::LPTIM3_OUT,
i => EXTSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `TIM1_CC1`"]
#[inline(always)]
pub fn is_tim1_cc1(&self) -> bool {
*self == EXTSELR::TIM1_CC1
}
#[doc = "Checks if the value of the field is `TIM1_CC2`"]
#[inline(always)]
pub fn is_tim1_cc2(&self) -> bool {
*self == EXTSELR::TIM1_CC2
}
#[doc = "Checks if the value of the field is `TIM1_CC3`"]
#[inline(always)]
pub fn is_tim1_cc3(&self) -> bool {
*self == EXTSELR::TIM1_CC3
}
#[doc = "Checks if the value of the field is `TIM2_CC2`"]
#[inline(always)]
pub fn is_tim2_cc2(&self) -> bool {
*self == EXTSELR::TIM2_CC2
}
#[doc = "Checks if the value of the field is `TIM3_TRGO`"]
#[inline(always)]
pub fn is_tim3_trgo(&self) -> bool {
*self == EXTSELR::TIM3_TRGO
}
#[doc = "Checks if the value of the field is `TIM4_CC4`"]
#[inline(always)]
pub fn is_tim4_cc4(&self) -> bool {
*self == EXTSELR::TIM4_CC4
}
#[doc = "Checks if the value of the field is `EXTI11`"]
#[inline(always)]
pub fn is_exti11(&self) -> bool {
*self == EXTSELR::EXTI11
}
#[doc = "Checks if the value of the field is `TIM8_TRGO`"]
#[inline(always)]
pub fn is_tim8_trgo(&self) -> bool {
*self == EXTSELR::TIM8_TRGO
}
#[doc = "Checks if the value of the field is `TIM8_TRGO2`"]
#[inline(always)]
pub fn is_tim8_trgo2(&self) -> bool {
*self == EXTSELR::TIM8_TRGO2
}
#[doc = "Checks if the value of the field is `TIM1_TRGO`"]
#[inline(always)]
pub fn is_tim1_trgo(&self) -> bool {
*self == EXTSELR::TIM1_TRGO
}
#[doc = "Checks if the value of the field is `TIM1_TRGO2`"]
#[inline(always)]
pub fn is_tim1_trgo2(&self) -> bool {
*self == EXTSELR::TIM1_TRGO2
}
#[doc = "Checks if the value of the field is `TIM2_TRGO`"]
#[inline(always)]
pub fn is_tim2_trgo(&self) -> bool {
*self == EXTSELR::TIM2_TRGO
}
#[doc = "Checks if the value of the field is `TIM4_TRGO`"]
#[inline(always)]
pub fn is_tim4_trgo(&self) -> bool {
*self == EXTSELR::TIM4_TRGO
}
#[doc = "Checks if the value of the field is `TIM6_TRGO`"]
#[inline(always)]
pub fn is_tim6_trgo(&self) -> bool {
*self == EXTSELR::TIM6_TRGO
}
#[doc = "Checks if the value of the field is `TIM15_TRGO`"]
#[inline(always)]
pub fn is_tim15_trgo(&self) -> bool {
*self == EXTSELR::TIM15_TRGO
}
#[doc = "Checks if the value of the field is `TIM3_CC4`"]
#[inline(always)]
pub fn is_tim3_cc4(&self) -> bool {
*self == EXTSELR::TIM3_CC4
}
#[doc = "Checks if the value of the field is `HRTIM1_ADCTRG1`"]
#[inline(always)]
pub fn is_hrtim1_adctrg1(&self) -> bool {
*self == EXTSELR::HRTIM1_ADCTRG1
}
#[doc = "Checks if the value of the field is `HRTIM1_ADCTRG3`"]
#[inline(always)]
pub fn is_hrtim1_adctrg3(&self) -> bool {
*self == EXTSELR::HRTIM1_ADCTRG3
}
#[doc = "Checks if the value of the field is `LPTIM1_OUT`"]
#[inline(always)]
pub fn is_lptim1_out(&self) -> bool {
*self == EXTSELR::LPTIM1_OUT
}
#[doc = "Checks if the value of the field is `LPTIM2_OUT`"]
#[inline(always)]
pub fn is_lptim2_out(&self) -> bool {
*self == EXTSELR::LPTIM2_OUT
}
#[doc = "Checks if the value of the field is `LPTIM3_OUT`"]
#[inline(always)]
pub fn is_lptim3_out(&self) -> bool {
*self == EXTSELR::LPTIM3_OUT
}
}
#[doc = "Values that can be written to the field `EXTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTSELW {
#[doc = "Timer 1 CC1 event"]
TIM1_CC1,
#[doc = "Timer 1 CC2 event"]
TIM1_CC2,
#[doc = "Timer 1 CC3 event"]
TIM1_CC3,
#[doc = "Timer 2 CC2 event"]
TIM2_CC2,
#[doc = "Timer 3 TRGO event"]
TIM3_TRGO,
#[doc = "Timer 4 CC4 event"]
TIM4_CC4,
#[doc = "EXTI line 11"]
EXTI11,
#[doc = "Timer 8 TRGO event"]
TIM8_TRGO,
#[doc = "Timer 8 TRGO2 event"]
TIM8_TRGO2,
#[doc = "Timer 1 TRGO event"]
TIM1_TRGO,
#[doc = "Timer 1 TRGO2 event"]
TIM1_TRGO2,
#[doc = "Timer 2 TRGO event"]
TIM2_TRGO,
#[doc = "Timer 4 TRGO event"]
TIM4_TRGO,
#[doc = "Timer 6 TRGO event"]
TIM6_TRGO,
#[doc = "Timer 15 TRGO event"]
TIM15_TRGO,
#[doc = "Timer 3 CC4 event"]
TIM3_CC4,
#[doc = "HRTIM1_ADCTRG1 event"]
HRTIM1_ADCTRG1,
#[doc = "HRTIM1_ADCTRG3 event"]
HRTIM1_ADCTRG3,
#[doc = "LPTIM1_OUT event"]
LPTIM1_OUT,
#[doc = "LPTIM2_OUT event"]
LPTIM2_OUT,
#[doc = "LPTIM3_OUT event"]
LPTIM3_OUT,
}
impl EXTSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
EXTSELW::TIM1_CC1 => 0,
EXTSELW::TIM1_CC2 => 1,
EXTSELW::TIM1_CC3 => 2,
EXTSELW::TIM2_CC2 => 3,
EXTSELW::TIM3_TRGO => 4,
EXTSELW::TIM4_CC4 => 5,
EXTSELW::EXTI11 => 6,
EXTSELW::TIM8_TRGO => 7,
EXTSELW::TIM8_TRGO2 => 8,
EXTSELW::TIM1_TRGO => 9,
EXTSELW::TIM1_TRGO2 => 10,
EXTSELW::TIM2_TRGO => 11,
EXTSELW::TIM4_TRGO => 12,
EXTSELW::TIM6_TRGO => 13,
EXTSELW::TIM15_TRGO => 14,
EXTSELW::TIM3_CC4 => 15,
EXTSELW::HRTIM1_ADCTRG1 => 16,
EXTSELW::HRTIM1_ADCTRG3 => 17,
EXTSELW::LPTIM1_OUT => 18,
EXTSELW::LPTIM2_OUT => 19,
EXTSELW::LPTIM3_OUT => 20,
}
}
}
#[doc = r"Proxy"]
pub struct _EXTSELW<'a> {
w: &'a mut W,
}
impl<'a> _EXTSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: EXTSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Timer 1 CC1 event"]
#[inline(always)]
pub fn tim1_cc1(self) -> &'a mut W {
self.variant(EXTSELW::TIM1_CC1)
}
#[doc = "Timer 1 CC2 event"]
#[inline(always)]
pub fn tim1_cc2(self) -> &'a mut W {
self.variant(EXTSELW::TIM1_CC2)
}
#[doc = "Timer 1 CC3 event"]
#[inline(always)]
pub fn tim1_cc3(self) -> &'a mut W {
self.variant(EXTSELW::TIM1_CC3)
}
#[doc = "Timer 2 CC2 event"]
#[inline(always)]
pub fn tim2_cc2(self) -> &'a mut W {
self.variant(EXTSELW::TIM2_CC2)
}
#[doc = "Timer 3 TRGO event"]
#[inline(always)]
pub fn tim3_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM3_TRGO)
}
#[doc = "Timer 4 CC4 event"]
#[inline(always)]
pub fn tim4_cc4(self) -> &'a mut W {
self.variant(EXTSELW::TIM4_CC4)
}
#[doc = "EXTI line 11"]
#[inline(always)]
pub fn exti11(self) -> &'a mut W {
self.variant(EXTSELW::EXTI11)
}
#[doc = "Timer 8 TRGO event"]
#[inline(always)]
pub fn tim8_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM8_TRGO)
}
#[doc = "Timer 8 TRGO2 event"]
#[inline(always)]
pub fn tim8_trgo2(self) -> &'a mut W {
self.variant(EXTSELW::TIM8_TRGO2)
}
#[doc = "Timer 1 TRGO event"]
#[inline(always)]
pub fn tim1_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM1_TRGO)
}
#[doc = "Timer 1 TRGO2 event"]
#[inline(always)]
pub fn tim1_trgo2(self) -> &'a mut W {
self.variant(EXTSELW::TIM1_TRGO2)
}
#[doc = "Timer 2 TRGO event"]
#[inline(always)]
pub fn tim2_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM2_TRGO)
}
#[doc = "Timer 4 TRGO event"]
#[inline(always)]
pub fn tim4_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM4_TRGO)
}
#[doc = "Timer 6 TRGO event"]
#[inline(always)]
pub fn tim6_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM6_TRGO)
}
#[doc = "Timer 15 TRGO event"]
#[inline(always)]
pub fn tim15_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM15_TRGO)
}
#[doc = "Timer 3 CC4 event"]
#[inline(always)]
pub fn tim3_cc4(self) -> &'a mut W {
self.variant(EXTSELW::TIM3_CC4)
}
#[doc = "HRTIM1_ADCTRG1 event"]
#[inline(always)]
pub fn hrtim1_adctrg1(self) -> &'a mut W {
self.variant(EXTSELW::HRTIM1_ADCTRG1)
}
#[doc = "HRTIM1_ADCTRG3 event"]
#[inline(always)]
pub fn hrtim1_adctrg3(self) -> &'a mut W {
self.variant(EXTSELW::HRTIM1_ADCTRG3)
}
#[doc = "LPTIM1_OUT event"]
#[inline(always)]
pub fn lptim1_out(self) -> &'a mut W {
self.variant(EXTSELW::LPTIM1_OUT)
}
#[doc = "LPTIM2_OUT event"]
#[inline(always)]
pub fn lptim2_out(self) -> &'a mut W {
self.variant(EXTSELW::LPTIM2_OUT)
}
#[doc = "LPTIM3_OUT event"]
#[inline(always)]
pub fn lptim3_out(self) -> &'a mut W {
self.variant(EXTSELW::LPTIM3_OUT)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 5);
self.w.bits |= ((value as u32) & 0x1f) << 5;
self.w
}
}
#[doc = "Possible values of the field `RES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RESR {
#[doc = "16-bit resolution"]
SIXTEENBIT,
#[doc = "14-bit resolution"]
FOURTEENBIT,
#[doc = "12-bit resolution"]
TWELVEBIT,
#[doc = "10-bit resolution"]
TENBIT,
#[doc = "8-bit resolution"]
EIGHTBIT,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl RESR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
RESR::SIXTEENBIT => 0,
RESR::FOURTEENBIT => 0x01,
RESR::TWELVEBIT => 0x02,
RESR::TENBIT => 0x03,
RESR::EIGHTBIT => 0x07,
RESR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> RESR {
match value {
0 => RESR::SIXTEENBIT,
1 => RESR::FOURTEENBIT,
2 => RESR::TWELVEBIT,
3 => RESR::TENBIT,
7 => RESR::EIGHTBIT,
i => RESR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `SIXTEENBIT`"]
#[inline(always)]
pub fn is_sixteen_bit(&self) -> bool {
*self == RESR::SIXTEENBIT
}
#[doc = "Checks if the value of the field is `FOURTEENBIT`"]
#[inline(always)]
pub fn is_fourteen_bit(&self) -> bool {
*self == RESR::FOURTEENBIT
}
#[doc = "Checks if the value of the field is `TWELVEBIT`"]
#[inline(always)]
pub fn is_twelve_bit(&self) -> bool {
*self == RESR::TWELVEBIT
}
#[doc = "Checks if the value of the field is `TENBIT`"]
#[inline(always)]
pub fn is_ten_bit(&self) -> bool {
*self == RESR::TENBIT
}
#[doc = "Checks if the value of the field is `EIGHTBIT`"]
#[inline(always)]
pub fn is_eight_bit(&self) -> bool {
*self == RESR::EIGHTBIT
}
}
#[doc = "Values that can be written to the field `RES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RESW {
#[doc = "16-bit resolution"]
SIXTEENBIT,
#[doc = "14-bit resolution"]
FOURTEENBIT,
#[doc = "12-bit resolution"]
TWELVEBIT,
#[doc = "10-bit resolution"]
TENBIT,
#[doc = "8-bit resolution"]
EIGHTBIT,
}
impl RESW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
RESW::SIXTEENBIT => 0,
RESW::FOURTEENBIT => 1,
RESW::TWELVEBIT => 2,
RESW::TENBIT => 3,
RESW::EIGHTBIT => 7,
}
}
}
#[doc = r"Proxy"]
pub struct _RESW<'a> {
w: &'a mut W,
}
impl<'a> _RESW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: RESW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "16-bit resolution"]
#[inline(always)]
pub fn sixteen_bit(self) -> &'a mut W {
self.variant(RESW::SIXTEENBIT)
}
#[doc = "14-bit resolution"]
#[inline(always)]
pub fn fourteen_bit(self) -> &'a mut W {
self.variant(RESW::FOURTEENBIT)
}
#[doc = "12-bit resolution"]
#[inline(always)]
pub fn twelve_bit(self) -> &'a mut W {
self.variant(RESW::TWELVEBIT)
}
#[doc = "10-bit resolution"]
#[inline(always)]
pub fn ten_bit(self) -> &'a mut W {
self.variant(RESW::TENBIT)
}
#[doc = "8-bit resolution"]
#[inline(always)]
pub fn eight_bit(self) -> &'a mut W {
self.variant(RESW::EIGHTBIT)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 2);
self.w.bits |= ((value as u32) & 0x07) << 2;
self.w
}
}
#[doc = r"Value of the field"]
pub struct DMNGTR {
bits: u8,
}
impl DMNGTR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _DMNGTW<'a> {
w: &'a mut W,
}
impl<'a> _DMNGTW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 0);
self.w.bits |= ((value as u32) & 0x03) << 0;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 31 - ADC group injected contexts queue disable"]
#[inline(always)]
pub fn jqdis(&self) -> JQDISR {
let bits = ((self.bits >> 31) & 0x01) != 0;
JQDISR { bits }
}
#[doc = "Bits 26:30 - ADC analog watchdog 1 monitored channel selection"]
#[inline(always)]
pub fn awdch1ch(&self) -> AWDCH1CHR {
let bits = ((self.bits >> 26) & 0x1f) as u8;
AWDCH1CHR { bits }
}
#[doc = "Bit 25 - ADC group injected automatic trigger mode"]
#[inline(always)]
pub fn jauto(&self) -> JAUTOR {
let bits = ((self.bits >> 25) & 0x01) != 0;
JAUTOR { bits }
}
#[doc = "Bit 24 - ADC analog watchdog 1 enable on scope ADC group injected"]
#[inline(always)]
pub fn jawd1en(&self) -> JAWD1ENR {
let bits = ((self.bits >> 24) & 0x01) != 0;
JAWD1ENR { bits }
}
#[doc = "Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular"]
#[inline(always)]
pub fn awd1en(&self) -> AWD1ENR {
let bits = ((self.bits >> 23) & 0x01) != 0;
AWD1ENR { bits }
}
#[doc = "Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels"]
#[inline(always)]
pub fn awd1sgl(&self) -> AWD1SGLR {
let bits = ((self.bits >> 22) & 0x01) != 0;
AWD1SGLR { bits }
}
#[doc = "Bit 21 - ADC group injected contexts queue mode"]
#[inline(always)]
pub fn jqm(&self) -> JQMR {
let bits = ((self.bits >> 21) & 0x01) != 0;
JQMR { bits }
}
#[doc = "Bit 20 - ADC group injected sequencer discontinuous mode"]
#[inline(always)]
pub fn jdiscen(&self) -> JDISCENR {
let bits = ((self.bits >> 20) & 0x01) != 0;
JDISCENR { bits }
}
#[doc = "Bits 17:19 - ADC group regular sequencer discontinuous number of ranks"]
#[inline(always)]
pub fn discnum(&self) -> DISCNUMR {
let bits = ((self.bits >> 17) & 0x07) as u8;
DISCNUMR { bits }
}
#[doc = "Bit 16 - ADC group regular sequencer discontinuous mode"]
#[inline(always)]
pub fn discen(&self) -> DISCENR {
let bits = ((self.bits >> 16) & 0x01) != 0;
DISCENR { bits }
}
#[doc = "Bit 14 - ADC low power auto wait"]
#[inline(always)]
pub fn autdly(&self) -> AUTDLYR {
let bits = ((self.bits >> 14) & 0x01) != 0;
AUTDLYR { bits }
}
#[doc = "Bit 13 - ADC group regular continuous conversion mode"]
#[inline(always)]
pub fn cont(&self) -> CONTR {
let bits = ((self.bits >> 13) & 0x01) != 0;
CONTR { bits }
}
#[doc = "Bit 12 - ADC group regular overrun configuration"]
#[inline(always)]
pub fn ovrmod(&self) -> OVRMODR {
let bits = ((self.bits >> 12) & 0x01) != 0;
OVRMODR { bits }
}
#[doc = "Bits 10:11 - ADC group regular external trigger polarity"]
#[inline(always)]
pub fn exten(&self) -> EXTENR {
EXTENR::_from(((self.bits >> 10) & 0x03) as u8)
}
#[doc = "Bits 5:9 - ADC group regular external trigger source"]
#[inline(always)]
pub fn extsel(&self) -> EXTSELR {
EXTSELR::_from(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bits 2:4 - ADC data resolution"]
#[inline(always)]
pub fn res(&self) -> RESR {
RESR::_from(((self.bits >> 2) & 0x07) as u8)
}
#[doc = "Bits 0:1 - ADC DMA transfer enable"]
#[inline(always)]
pub fn dmngt(&self) -> DMNGTR {
let bits = ((self.bits >> 0) & 0x03) as u8;
DMNGTR { bits }
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 31 - ADC group injected contexts queue disable"]
#[inline(always)]
pub fn jqdis(&mut self) -> _JQDISW {
_JQDISW { w: self }
}
#[doc = "Bits 26:30 - ADC analog watchdog 1 monitored channel selection"]
#[inline(always)]
pub fn awdch1ch(&mut self) -> _AWDCH1CHW {
_AWDCH1CHW { w: self }
}
#[doc = "Bit 25 - ADC group injected automatic trigger mode"]
#[inline(always)]
pub fn jauto(&mut self) -> _JAUTOW {
_JAUTOW { w: self }
}
#[doc = "Bit 24 - ADC analog watchdog 1 enable on scope ADC group injected"]
#[inline(always)]
pub fn jawd1en(&mut self) -> _JAWD1ENW {
_JAWD1ENW { w: self }
}
#[doc = "Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular"]
#[inline(always)]
pub fn awd1en(&mut self) -> _AWD1ENW {
_AWD1ENW { w: self }
}
#[doc = "Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels"]
#[inline(always)]
pub fn awd1sgl(&mut self) -> _AWD1SGLW {
_AWD1SGLW { w: self }
}
#[doc = "Bit 21 - ADC group injected contexts queue mode"]
#[inline(always)]
pub fn jqm(&mut self) -> _JQMW {
_JQMW { w: self }
}
#[doc = "Bit 20 - ADC group injected sequencer discontinuous mode"]
#[inline(always)]
pub fn jdiscen(&mut self) -> _JDISCENW {
_JDISCENW { w: self }
}
#[doc = "Bits 17:19 - ADC group regular sequencer discontinuous number of ranks"]
#[inline(always)]
pub fn discnum(&mut self) -> _DISCNUMW {
_DISCNUMW { w: self }
}
#[doc = "Bit 16 - ADC group regular sequencer discontinuous mode"]
#[inline(always)]
pub fn discen(&mut self) -> _DISCENW {
_DISCENW { w: self }
}
#[doc = "Bit 14 - ADC low power auto wait"]
#[inline(always)]
pub fn autdly(&mut self) -> _AUTDLYW {
_AUTDLYW { w: self }
}
#[doc = "Bit 13 - ADC group regular continuous conversion mode"]
#[inline(always)]
pub fn cont(&mut self) -> _CONTW {
_CONTW { w: self }
}
#[doc = "Bit 12 - ADC group regular overrun configuration"]
#[inline(always)]
pub fn ovrmod(&mut self) -> _OVRMODW {
_OVRMODW { w: self }
}
#[doc = "Bits 10:11 - ADC group regular external trigger polarity"]
#[inline(always)]
pub fn exten(&mut self) -> _EXTENW {
_EXTENW { w: self }
}
#[doc = "Bits 5:9 - ADC group regular external trigger source"]
#[inline(always)]
pub fn extsel(&mut self) -> _EXTSELW {
_EXTSELW { w: self }
}
#[doc = "Bits 2:4 - ADC data resolution"]
#[inline(always)]
pub fn res(&mut self) -> _RESW {
_RESW { w: self }
}
#[doc = "Bits 0:1 - ADC DMA transfer enable"]
#[inline(always)]
pub fn dmngt(&mut self) -> _DMNGTW {
_DMNGTW { w: self }
}
}