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#[doc = r"Value read from the register"] pub struct R { bits: u32, } #[doc = r"Value to write to the register"] pub struct W { bits: u32, } impl super::PLLCKSELR { #[doc = r"Modifies the contents of the register"] #[inline(always)] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set(f(&R { bits }, &mut W { bits }).bits); } #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r"Writes to the register"] #[inline(always)] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { self.register.set( f(&mut W { bits: Self::reset_value(), }) .bits, ); } #[doc = r"Reset value of the register"] #[inline(always)] pub const fn reset_value() -> u32 { 0x0202_0200 } #[doc = r"Writes the reset value to the register"] #[inline(always)] pub fn reset(&self) { self.register.set(Self::reset_value()) } } #[doc = "Possible values of the field `PLLSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PLLSRCR { #[doc = "HSI selected as PLL clock"] HSI, #[doc = "CSI selected as PLL clock"] CSI, #[doc = "HSE selected as PLL clock"] HSE, #[doc = "No clock sent to DIVMx dividers and PLLs"] NONE, } impl PLLSRCR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { match *self { PLLSRCR::HSI => 0, PLLSRCR::CSI => 0x01, PLLSRCR::HSE => 0x02, PLLSRCR::NONE => 0x03, } } #[allow(missing_docs)] #[doc(hidden)] #[inline(always)] pub fn _from(value: u8) -> PLLSRCR { match value { 0 => PLLSRCR::HSI, 1 => PLLSRCR::CSI, 2 => PLLSRCR::HSE, 3 => PLLSRCR::NONE, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `HSI`"] #[inline(always)] pub fn is_hsi(&self) -> bool { *self == PLLSRCR::HSI } #[doc = "Checks if the value of the field is `CSI`"] #[inline(always)] pub fn is_csi(&self) -> bool { *self == PLLSRCR::CSI } #[doc = "Checks if the value of the field is `HSE`"] #[inline(always)] pub fn is_hse(&self) -> bool { *self == PLLSRCR::HSE } #[doc = "Checks if the value of the field is `NONE`"] #[inline(always)] pub fn is_none(&self) -> bool { *self == PLLSRCR::NONE } } #[doc = "Values that can be written to the field `PLLSRC`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PLLSRCW { #[doc = "HSI selected as PLL clock"] HSI, #[doc = "CSI selected as PLL clock"] CSI, #[doc = "HSE selected as PLL clock"] HSE, #[doc = "No clock sent to DIVMx dividers and PLLs"] NONE, } impl PLLSRCW { #[allow(missing_docs)] #[doc(hidden)] #[inline(always)] pub fn _bits(&self) -> u8 { match *self { PLLSRCW::HSI => 0, PLLSRCW::CSI => 1, PLLSRCW::HSE => 2, PLLSRCW::NONE => 3, } } } #[doc = r"Proxy"] pub struct _PLLSRCW<'a> { w: &'a mut W, } impl<'a> _PLLSRCW<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: PLLSRCW) -> &'a mut W { { self.bits(variant._bits()) } } #[doc = "HSI selected as PLL clock"] #[inline(always)] pub fn hsi(self) -> &'a mut W { self.variant(PLLSRCW::HSI) } #[doc = "CSI selected as PLL clock"] #[inline(always)] pub fn csi(self) -> &'a mut W { self.variant(PLLSRCW::CSI) } #[doc = "HSE selected as PLL clock"] #[inline(always)] pub fn hse(self) -> &'a mut W { self.variant(PLLSRCW::HSE) } #[doc = "No clock sent to DIVMx dividers and PLLs"] #[inline(always)] pub fn none(self) -> &'a mut W { self.variant(PLLSRCW::NONE) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x03 << 0); self.w.bits |= ((value as u32) & 0x03) << 0; self.w } } #[doc = r"Value of the field"] pub struct DIVM1R { bits: u8, } impl DIVM1R { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _DIVM1W<'a> { w: &'a mut W, } impl<'a> _DIVM1W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x3f << 4); self.w.bits |= ((value as u32) & 0x3f) << 4; self.w } } #[doc = r"Value of the field"] pub struct DIVM2R { bits: u8, } impl DIVM2R { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _DIVM2W<'a> { w: &'a mut W, } impl<'a> _DIVM2W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x3f << 12); self.w.bits |= ((value as u32) & 0x3f) << 12; self.w } } #[doc = r"Value of the field"] pub struct DIVM3R { bits: u8, } impl DIVM3R { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _DIVM3W<'a> { w: &'a mut W, } impl<'a> _DIVM3W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x3f << 20); self.w.bits |= ((value as u32) & 0x3f) << 20; self.w } } impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bits 0:1 - DIVMx and PLLs clock source selection"] #[inline(always)] pub fn pllsrc(&self) -> PLLSRCR { PLLSRCR::_from(((self.bits >> 0) & 0x03) as u8) } #[doc = "Bits 4:9 - Prescaler for PLL1"] #[inline(always)] pub fn divm1(&self) -> DIVM1R { let bits = ((self.bits >> 4) & 0x3f) as u8; DIVM1R { bits } } #[doc = "Bits 12:17 - Prescaler for PLL2"] #[inline(always)] pub fn divm2(&self) -> DIVM2R { let bits = ((self.bits >> 12) & 0x3f) as u8; DIVM2R { bits } } #[doc = "Bits 20:25 - Prescaler for PLL3"] #[inline(always)] pub fn divm3(&self) -> DIVM3R { let bits = ((self.bits >> 20) & 0x3f) as u8; DIVM3R { bits } } } impl W { #[doc = r"Writes raw bits to the register"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bits 0:1 - DIVMx and PLLs clock source selection"] #[inline(always)] pub fn pllsrc(&mut self) -> _PLLSRCW { _PLLSRCW { w: self } } #[doc = "Bits 4:9 - Prescaler for PLL1"] #[inline(always)] pub fn divm1(&mut self) -> _DIVM1W { _DIVM1W { w: self } } #[doc = "Bits 12:17 - Prescaler for PLL2"] #[inline(always)] pub fn divm2(&mut self) -> _DIVM2W { _DIVM2W { w: self } } #[doc = "Bits 20:25 - Prescaler for PLL3"] #[inline(always)] pub fn divm3(&mut self) -> _DIVM3W { _DIVM3W { w: self } } }