#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CCR {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `DMAREQ_ID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAREQ_IDR {
#[doc = "No signal selected as request input"]
NONE,
#[doc = "Signal `dmamux2_req_gen0` selected as request input"]
DMAMUX2_REQ_GEN0,
#[doc = "Signal `dmamux2_req_gen1` selected as request input"]
DMAMUX2_REQ_GEN1,
#[doc = "Signal `dmamux2_req_gen2` selected as request input"]
DMAMUX2_REQ_GEN2,
#[doc = "Signal `dmamux2_req_gen3` selected as request input"]
DMAMUX2_REQ_GEN3,
#[doc = "Signal `dmamux2_req_gen4` selected as request input"]
DMAMUX2_REQ_GEN4,
#[doc = "Signal `dmamux2_req_gen5` selected as request input"]
DMAMUX2_REQ_GEN5,
#[doc = "Signal `dmamux2_req_gen6` selected as request input"]
DMAMUX2_REQ_GEN6,
#[doc = "Signal `dmamux2_req_gen7` selected as request input"]
DMAMUX2_REQ_GEN7,
#[doc = "Signal `lpuart1_rx_dma` selected as request input"]
LPUART1_RX_DMA,
#[doc = "Signal `lpuart1_tx_dma` selected as request input"]
LPUART1_TX_DMA,
#[doc = "Signal `spi6_rx_dma` selected as request input"]
SPI6_RX_DMA,
#[doc = "Signal `spi6_tx_dma` selected as request input"]
SPI6_TX_DMA,
#[doc = "Signal `i2c4_rx_dma` selected as request input"]
I2C4_RX_DMA,
#[doc = "Signal `i2c4_tx_dma` selected as request input"]
I2C4_TX_DMA,
#[doc = "Signal `sai4_a_dma` selected as request input"]
SAI4_A_DMA,
#[doc = "Signal `sai4_b_dma` selected as request input"]
SAI4_B_DMA,
#[doc = "Signal `adc3_dma` selected as request input"]
ADC3_DMA,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl DMAREQ_IDR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
DMAREQ_IDR::NONE => 0,
DMAREQ_IDR::DMAMUX2_REQ_GEN0 => 0x01,
DMAREQ_IDR::DMAMUX2_REQ_GEN1 => 0x02,
DMAREQ_IDR::DMAMUX2_REQ_GEN2 => 0x03,
DMAREQ_IDR::DMAMUX2_REQ_GEN3 => 0x04,
DMAREQ_IDR::DMAMUX2_REQ_GEN4 => 0x05,
DMAREQ_IDR::DMAMUX2_REQ_GEN5 => 0x06,
DMAREQ_IDR::DMAMUX2_REQ_GEN6 => 0x07,
DMAREQ_IDR::DMAMUX2_REQ_GEN7 => 0x08,
DMAREQ_IDR::LPUART1_RX_DMA => 0x09,
DMAREQ_IDR::LPUART1_TX_DMA => 0x0a,
DMAREQ_IDR::SPI6_RX_DMA => 0x0b,
DMAREQ_IDR::SPI6_TX_DMA => 0x0c,
DMAREQ_IDR::I2C4_RX_DMA => 0x0d,
DMAREQ_IDR::I2C4_TX_DMA => 0x0e,
DMAREQ_IDR::SAI4_A_DMA => 0x0f,
DMAREQ_IDR::SAI4_B_DMA => 0x10,
DMAREQ_IDR::ADC3_DMA => 0x11,
DMAREQ_IDR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> DMAREQ_IDR {
match value {
0 => DMAREQ_IDR::NONE,
1 => DMAREQ_IDR::DMAMUX2_REQ_GEN0,
2 => DMAREQ_IDR::DMAMUX2_REQ_GEN1,
3 => DMAREQ_IDR::DMAMUX2_REQ_GEN2,
4 => DMAREQ_IDR::DMAMUX2_REQ_GEN3,
5 => DMAREQ_IDR::DMAMUX2_REQ_GEN4,
6 => DMAREQ_IDR::DMAMUX2_REQ_GEN5,
7 => DMAREQ_IDR::DMAMUX2_REQ_GEN6,
8 => DMAREQ_IDR::DMAMUX2_REQ_GEN7,
9 => DMAREQ_IDR::LPUART1_RX_DMA,
10 => DMAREQ_IDR::LPUART1_TX_DMA,
11 => DMAREQ_IDR::SPI6_RX_DMA,
12 => DMAREQ_IDR::SPI6_TX_DMA,
13 => DMAREQ_IDR::I2C4_RX_DMA,
14 => DMAREQ_IDR::I2C4_TX_DMA,
15 => DMAREQ_IDR::SAI4_A_DMA,
16 => DMAREQ_IDR::SAI4_B_DMA,
17 => DMAREQ_IDR::ADC3_DMA,
i => DMAREQ_IDR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `NONE`"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == DMAREQ_IDR::NONE
}
#[doc = "Checks if the value of the field is `DMAMUX2_REQ_GEN0`"]
#[inline(always)]
pub fn is_dmamux2_req_gen0(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX2_REQ_GEN0
}
#[doc = "Checks if the value of the field is `DMAMUX2_REQ_GEN1`"]
#[inline(always)]
pub fn is_dmamux2_req_gen1(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX2_REQ_GEN1
}
#[doc = "Checks if the value of the field is `DMAMUX2_REQ_GEN2`"]
#[inline(always)]
pub fn is_dmamux2_req_gen2(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX2_REQ_GEN2
}
#[doc = "Checks if the value of the field is `DMAMUX2_REQ_GEN3`"]
#[inline(always)]
pub fn is_dmamux2_req_gen3(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX2_REQ_GEN3
}
#[doc = "Checks if the value of the field is `DMAMUX2_REQ_GEN4`"]
#[inline(always)]
pub fn is_dmamux2_req_gen4(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX2_REQ_GEN4
}
#[doc = "Checks if the value of the field is `DMAMUX2_REQ_GEN5`"]
#[inline(always)]
pub fn is_dmamux2_req_gen5(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX2_REQ_GEN5
}
#[doc = "Checks if the value of the field is `DMAMUX2_REQ_GEN6`"]
#[inline(always)]
pub fn is_dmamux2_req_gen6(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX2_REQ_GEN6
}
#[doc = "Checks if the value of the field is `DMAMUX2_REQ_GEN7`"]
#[inline(always)]
pub fn is_dmamux2_req_gen7(&self) -> bool {
*self == DMAREQ_IDR::DMAMUX2_REQ_GEN7
}
#[doc = "Checks if the value of the field is `LPUART1_RX_DMA`"]
#[inline(always)]
pub fn is_lpuart1_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::LPUART1_RX_DMA
}
#[doc = "Checks if the value of the field is `LPUART1_TX_DMA`"]
#[inline(always)]
pub fn is_lpuart1_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::LPUART1_TX_DMA
}
#[doc = "Checks if the value of the field is `SPI6_RX_DMA`"]
#[inline(always)]
pub fn is_spi6_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI6_RX_DMA
}
#[doc = "Checks if the value of the field is `SPI6_TX_DMA`"]
#[inline(always)]
pub fn is_spi6_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::SPI6_TX_DMA
}
#[doc = "Checks if the value of the field is `I2C4_RX_DMA`"]
#[inline(always)]
pub fn is_i2c4_rx_dma(&self) -> bool {
*self == DMAREQ_IDR::I2C4_RX_DMA
}
#[doc = "Checks if the value of the field is `I2C4_TX_DMA`"]
#[inline(always)]
pub fn is_i2c4_tx_dma(&self) -> bool {
*self == DMAREQ_IDR::I2C4_TX_DMA
}
#[doc = "Checks if the value of the field is `SAI4_A_DMA`"]
#[inline(always)]
pub fn is_sai4_a_dma(&self) -> bool {
*self == DMAREQ_IDR::SAI4_A_DMA
}
#[doc = "Checks if the value of the field is `SAI4_B_DMA`"]
#[inline(always)]
pub fn is_sai4_b_dma(&self) -> bool {
*self == DMAREQ_IDR::SAI4_B_DMA
}
#[doc = "Checks if the value of the field is `ADC3_DMA`"]
#[inline(always)]
pub fn is_adc3_dma(&self) -> bool {
*self == DMAREQ_IDR::ADC3_DMA
}
}
#[doc = "Values that can be written to the field `DMAREQ_ID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAREQ_IDW {
#[doc = "No signal selected as request input"]
NONE,
#[doc = "Signal `dmamux2_req_gen0` selected as request input"]
DMAMUX2_REQ_GEN0,
#[doc = "Signal `dmamux2_req_gen1` selected as request input"]
DMAMUX2_REQ_GEN1,
#[doc = "Signal `dmamux2_req_gen2` selected as request input"]
DMAMUX2_REQ_GEN2,
#[doc = "Signal `dmamux2_req_gen3` selected as request input"]
DMAMUX2_REQ_GEN3,
#[doc = "Signal `dmamux2_req_gen4` selected as request input"]
DMAMUX2_REQ_GEN4,
#[doc = "Signal `dmamux2_req_gen5` selected as request input"]
DMAMUX2_REQ_GEN5,
#[doc = "Signal `dmamux2_req_gen6` selected as request input"]
DMAMUX2_REQ_GEN6,
#[doc = "Signal `dmamux2_req_gen7` selected as request input"]
DMAMUX2_REQ_GEN7,
#[doc = "Signal `lpuart1_rx_dma` selected as request input"]
LPUART1_RX_DMA,
#[doc = "Signal `lpuart1_tx_dma` selected as request input"]
LPUART1_TX_DMA,
#[doc = "Signal `spi6_rx_dma` selected as request input"]
SPI6_RX_DMA,
#[doc = "Signal `spi6_tx_dma` selected as request input"]
SPI6_TX_DMA,
#[doc = "Signal `i2c4_rx_dma` selected as request input"]
I2C4_RX_DMA,
#[doc = "Signal `i2c4_tx_dma` selected as request input"]
I2C4_TX_DMA,
#[doc = "Signal `sai4_a_dma` selected as request input"]
SAI4_A_DMA,
#[doc = "Signal `sai4_b_dma` selected as request input"]
SAI4_B_DMA,
#[doc = "Signal `adc3_dma` selected as request input"]
ADC3_DMA,
}
impl DMAREQ_IDW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
DMAREQ_IDW::NONE => 0,
DMAREQ_IDW::DMAMUX2_REQ_GEN0 => 1,
DMAREQ_IDW::DMAMUX2_REQ_GEN1 => 2,
DMAREQ_IDW::DMAMUX2_REQ_GEN2 => 3,
DMAREQ_IDW::DMAMUX2_REQ_GEN3 => 4,
DMAREQ_IDW::DMAMUX2_REQ_GEN4 => 5,
DMAREQ_IDW::DMAMUX2_REQ_GEN5 => 6,
DMAREQ_IDW::DMAMUX2_REQ_GEN6 => 7,
DMAREQ_IDW::DMAMUX2_REQ_GEN7 => 8,
DMAREQ_IDW::LPUART1_RX_DMA => 9,
DMAREQ_IDW::LPUART1_TX_DMA => 10,
DMAREQ_IDW::SPI6_RX_DMA => 11,
DMAREQ_IDW::SPI6_TX_DMA => 12,
DMAREQ_IDW::I2C4_RX_DMA => 13,
DMAREQ_IDW::I2C4_TX_DMA => 14,
DMAREQ_IDW::SAI4_A_DMA => 15,
DMAREQ_IDW::SAI4_B_DMA => 16,
DMAREQ_IDW::ADC3_DMA => 17,
}
}
}
#[doc = r"Proxy"]
pub struct _DMAREQ_IDW<'a> {
w: &'a mut W,
}
impl<'a> _DMAREQ_IDW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DMAREQ_IDW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "No signal selected as request input"]
#[inline(always)]
pub fn none(self) -> &'a mut W {
self.variant(DMAREQ_IDW::NONE)
}
#[doc = "Signal `dmamux2_req_gen0` selected as request input"]
#[inline(always)]
pub fn dmamux2_req_gen0(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX2_REQ_GEN0)
}
#[doc = "Signal `dmamux2_req_gen1` selected as request input"]
#[inline(always)]
pub fn dmamux2_req_gen1(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX2_REQ_GEN1)
}
#[doc = "Signal `dmamux2_req_gen2` selected as request input"]
#[inline(always)]
pub fn dmamux2_req_gen2(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX2_REQ_GEN2)
}
#[doc = "Signal `dmamux2_req_gen3` selected as request input"]
#[inline(always)]
pub fn dmamux2_req_gen3(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX2_REQ_GEN3)
}
#[doc = "Signal `dmamux2_req_gen4` selected as request input"]
#[inline(always)]
pub fn dmamux2_req_gen4(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX2_REQ_GEN4)
}
#[doc = "Signal `dmamux2_req_gen5` selected as request input"]
#[inline(always)]
pub fn dmamux2_req_gen5(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX2_REQ_GEN5)
}
#[doc = "Signal `dmamux2_req_gen6` selected as request input"]
#[inline(always)]
pub fn dmamux2_req_gen6(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX2_REQ_GEN6)
}
#[doc = "Signal `dmamux2_req_gen7` selected as request input"]
#[inline(always)]
pub fn dmamux2_req_gen7(self) -> &'a mut W {
self.variant(DMAREQ_IDW::DMAMUX2_REQ_GEN7)
}
#[doc = "Signal `lpuart1_rx_dma` selected as request input"]
#[inline(always)]
pub fn lpuart1_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::LPUART1_RX_DMA)
}
#[doc = "Signal `lpuart1_tx_dma` selected as request input"]
#[inline(always)]
pub fn lpuart1_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::LPUART1_TX_DMA)
}
#[doc = "Signal `spi6_rx_dma` selected as request input"]
#[inline(always)]
pub fn spi6_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI6_RX_DMA)
}
#[doc = "Signal `spi6_tx_dma` selected as request input"]
#[inline(always)]
pub fn spi6_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SPI6_TX_DMA)
}
#[doc = "Signal `i2c4_rx_dma` selected as request input"]
#[inline(always)]
pub fn i2c4_rx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::I2C4_RX_DMA)
}
#[doc = "Signal `i2c4_tx_dma` selected as request input"]
#[inline(always)]
pub fn i2c4_tx_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::I2C4_TX_DMA)
}
#[doc = "Signal `sai4_a_dma` selected as request input"]
#[inline(always)]
pub fn sai4_a_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SAI4_A_DMA)
}
#[doc = "Signal `sai4_b_dma` selected as request input"]
#[inline(always)]
pub fn sai4_b_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::SAI4_B_DMA)
}
#[doc = "Signal `adc3_dma` selected as request input"]
#[inline(always)]
pub fn adc3_dma(self) -> &'a mut W {
self.variant(DMAREQ_IDW::ADC3_DMA)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0xff << 0);
self.w.bits |= ((value as u32) & 0xff) << 0;
self.w
}
}
#[doc = "Possible values of the field `SOIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOIER {
#[doc = "Synchronization overrun interrupt disabled"]
DISABLED,
#[doc = "Synchronization overrun interrupt enabled"]
ENABLED,
}
impl SOIER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SOIER::DISABLED => false,
SOIER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SOIER {
match value {
false => SOIER::DISABLED,
true => SOIER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SOIER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SOIER::ENABLED
}
}
#[doc = "Values that can be written to the field `SOIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOIEW {
#[doc = "Synchronization overrun interrupt disabled"]
DISABLED,
#[doc = "Synchronization overrun interrupt enabled"]
ENABLED,
}
impl SOIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SOIEW::DISABLED => false,
SOIEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SOIEW<'a> {
w: &'a mut W,
}
impl<'a> _SOIEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SOIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Synchronization overrun interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SOIEW::DISABLED)
}
#[doc = "Synchronization overrun interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SOIEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 8);
self.w.bits |= ((value as u32) & 0x01) << 8;
self.w
}
}
#[doc = "Possible values of the field `EGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EGER {
#[doc = "Event generation disabled"]
DISABLED,
#[doc = "Event generation enabled"]
ENABLED,
}
impl EGER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
EGER::DISABLED => false,
EGER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> EGER {
match value {
false => EGER::DISABLED,
true => EGER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == EGER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == EGER::ENABLED
}
}
#[doc = "Values that can be written to the field `EGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EGEW {
#[doc = "Event generation disabled"]
DISABLED,
#[doc = "Event generation enabled"]
ENABLED,
}
impl EGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
EGEW::DISABLED => false,
EGEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _EGEW<'a> {
w: &'a mut W,
}
impl<'a> _EGEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: EGEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Event generation disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(EGEW::DISABLED)
}
#[doc = "Event generation enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(EGEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 9);
self.w.bits |= ((value as u32) & 0x01) << 9;
self.w
}
}
#[doc = "Possible values of the field `SE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SER {
#[doc = "Synchronization disabled"]
DISABLED,
#[doc = "Synchronization enabled"]
ENABLED,
}
impl SER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SER::DISABLED => false,
SER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SER {
match value {
false => SER::DISABLED,
true => SER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SER::ENABLED
}
}
#[doc = "Values that can be written to the field `SE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SEW {
#[doc = "Synchronization disabled"]
DISABLED,
#[doc = "Synchronization enabled"]
ENABLED,
}
impl SEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SEW::DISABLED => false,
SEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SEW<'a> {
w: &'a mut W,
}
impl<'a> _SEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Synchronization disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SEW::DISABLED)
}
#[doc = "Synchronization enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 16);
self.w.bits |= ((value as u32) & 0x01) << 16;
self.w
}
}
#[doc = "Possible values of the field `SPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPOLR {
#[doc = "No event, i.e. no synchronization nor detection"]
NOEDGE,
#[doc = "Rising edge"]
RISINGEDGE,
#[doc = "Falling edge"]
FALLINGEDGE,
#[doc = "Rising and falling edges"]
BOTHEDGES,
}
impl SPOLR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SPOLR::NOEDGE => 0,
SPOLR::RISINGEDGE => 0x01,
SPOLR::FALLINGEDGE => 0x02,
SPOLR::BOTHEDGES => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SPOLR {
match value {
0 => SPOLR::NOEDGE,
1 => SPOLR::RISINGEDGE,
2 => SPOLR::FALLINGEDGE,
3 => SPOLR::BOTHEDGES,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `NOEDGE`"]
#[inline(always)]
pub fn is_no_edge(&self) -> bool {
*self == SPOLR::NOEDGE
}
#[doc = "Checks if the value of the field is `RISINGEDGE`"]
#[inline(always)]
pub fn is_rising_edge(&self) -> bool {
*self == SPOLR::RISINGEDGE
}
#[doc = "Checks if the value of the field is `FALLINGEDGE`"]
#[inline(always)]
pub fn is_falling_edge(&self) -> bool {
*self == SPOLR::FALLINGEDGE
}
#[doc = "Checks if the value of the field is `BOTHEDGES`"]
#[inline(always)]
pub fn is_both_edges(&self) -> bool {
*self == SPOLR::BOTHEDGES
}
}
#[doc = "Values that can be written to the field `SPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPOLW {
#[doc = "No event, i.e. no synchronization nor detection"]
NOEDGE,
#[doc = "Rising edge"]
RISINGEDGE,
#[doc = "Falling edge"]
FALLINGEDGE,
#[doc = "Rising and falling edges"]
BOTHEDGES,
}
impl SPOLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SPOLW::NOEDGE => 0,
SPOLW::RISINGEDGE => 1,
SPOLW::FALLINGEDGE => 2,
SPOLW::BOTHEDGES => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _SPOLW<'a> {
w: &'a mut W,
}
impl<'a> _SPOLW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SPOLW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "No event, i.e. no synchronization nor detection"]
#[inline(always)]
pub fn no_edge(self) -> &'a mut W {
self.variant(SPOLW::NOEDGE)
}
#[doc = "Rising edge"]
#[inline(always)]
pub fn rising_edge(self) -> &'a mut W {
self.variant(SPOLW::RISINGEDGE)
}
#[doc = "Falling edge"]
#[inline(always)]
pub fn falling_edge(self) -> &'a mut W {
self.variant(SPOLW::FALLINGEDGE)
}
#[doc = "Rising and falling edges"]
#[inline(always)]
pub fn both_edges(self) -> &'a mut W {
self.variant(SPOLW::BOTHEDGES)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 17);
self.w.bits |= ((value as u32) & 0x03) << 17;
self.w
}
}
#[doc = r"Value of the field"]
pub struct NBREQR {
bits: u8,
}
impl NBREQR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _NBREQW<'a> {
w: &'a mut W,
}
impl<'a> _NBREQW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 19);
self.w.bits |= ((value as u32) & 0x1f) << 19;
self.w
}
}
#[doc = "Possible values of the field `SYNC_ID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYNC_IDR {
#[doc = "Signal `dmamux2_evt0` selected as synchronization input"]
DMAMUX2_EVT0,
#[doc = "Signal `dmamux2_evt1` selected as synchronization input"]
DMAMUX2_EVT1,
#[doc = "Signal `dmamux2_evt2` selected as synchronization input"]
DMAMUX2_EVT2,
#[doc = "Signal `dmamux2_evt3` selected as synchronization input"]
DMAMUX2_EVT3,
#[doc = "Signal `dmamux2_evt4` selected as synchronization input"]
DMAMUX2_EVT4,
#[doc = "Signal `dmamux2_evt5` selected as synchronization input"]
DMAMUX2_EVT5,
#[doc = "Signal `lpuart1_rx_wkup` selected as synchronization input"]
LPUART1_RX_WKUP,
#[doc = "Signal `lpuart1_tx_wkup` selected as synchronization input"]
LPUART1_TX_WKUP,
#[doc = "Signal `lptim2_out` selected as synchronization input"]
LPTIM2_OUT,
#[doc = "Signal `lptim3_out` selected as synchronization input"]
LPTIM3_OUT,
#[doc = "Signal `i2c4_wkup` selected as synchronization input"]
I2C4_WKUP,
#[doc = "Signal `spi6_wkup` selected as synchronization input"]
SPI6_WKUP,
#[doc = "Signal `comp1_out` selected as synchronization input"]
COMP1_OUT,
#[doc = "Signal `rtc_wkup` selected as synchronization input"]
RTC_WKUP,
#[doc = "Signal `syscfg_exti0_mux` selected as synchronization input"]
SYSCFG_EXTI0_MUX,
#[doc = "Signal `syscfg_exti2_mux` selected as synchronization input"]
SYSCFG_EXTI2_MUX,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl SYNC_IDR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SYNC_IDR::DMAMUX2_EVT0 => 0,
SYNC_IDR::DMAMUX2_EVT1 => 0x01,
SYNC_IDR::DMAMUX2_EVT2 => 0x02,
SYNC_IDR::DMAMUX2_EVT3 => 0x03,
SYNC_IDR::DMAMUX2_EVT4 => 0x04,
SYNC_IDR::DMAMUX2_EVT5 => 0x05,
SYNC_IDR::LPUART1_RX_WKUP => 0x06,
SYNC_IDR::LPUART1_TX_WKUP => 0x07,
SYNC_IDR::LPTIM2_OUT => 0x08,
SYNC_IDR::LPTIM3_OUT => 0x09,
SYNC_IDR::I2C4_WKUP => 0x0a,
SYNC_IDR::SPI6_WKUP => 0x0b,
SYNC_IDR::COMP1_OUT => 0x0c,
SYNC_IDR::RTC_WKUP => 0x0d,
SYNC_IDR::SYSCFG_EXTI0_MUX => 0x0e,
SYNC_IDR::SYSCFG_EXTI2_MUX => 0x0f,
SYNC_IDR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SYNC_IDR {
match value {
0 => SYNC_IDR::DMAMUX2_EVT0,
1 => SYNC_IDR::DMAMUX2_EVT1,
2 => SYNC_IDR::DMAMUX2_EVT2,
3 => SYNC_IDR::DMAMUX2_EVT3,
4 => SYNC_IDR::DMAMUX2_EVT4,
5 => SYNC_IDR::DMAMUX2_EVT5,
6 => SYNC_IDR::LPUART1_RX_WKUP,
7 => SYNC_IDR::LPUART1_TX_WKUP,
8 => SYNC_IDR::LPTIM2_OUT,
9 => SYNC_IDR::LPTIM3_OUT,
10 => SYNC_IDR::I2C4_WKUP,
11 => SYNC_IDR::SPI6_WKUP,
12 => SYNC_IDR::COMP1_OUT,
13 => SYNC_IDR::RTC_WKUP,
14 => SYNC_IDR::SYSCFG_EXTI0_MUX,
15 => SYNC_IDR::SYSCFG_EXTI2_MUX,
i => SYNC_IDR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT0`"]
#[inline(always)]
pub fn is_dmamux2_evt0(&self) -> bool {
*self == SYNC_IDR::DMAMUX2_EVT0
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT1`"]
#[inline(always)]
pub fn is_dmamux2_evt1(&self) -> bool {
*self == SYNC_IDR::DMAMUX2_EVT1
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT2`"]
#[inline(always)]
pub fn is_dmamux2_evt2(&self) -> bool {
*self == SYNC_IDR::DMAMUX2_EVT2
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT3`"]
#[inline(always)]
pub fn is_dmamux2_evt3(&self) -> bool {
*self == SYNC_IDR::DMAMUX2_EVT3
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT4`"]
#[inline(always)]
pub fn is_dmamux2_evt4(&self) -> bool {
*self == SYNC_IDR::DMAMUX2_EVT4
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT5`"]
#[inline(always)]
pub fn is_dmamux2_evt5(&self) -> bool {
*self == SYNC_IDR::DMAMUX2_EVT5
}
#[doc = "Checks if the value of the field is `LPUART1_RX_WKUP`"]
#[inline(always)]
pub fn is_lpuart1_rx_wkup(&self) -> bool {
*self == SYNC_IDR::LPUART1_RX_WKUP
}
#[doc = "Checks if the value of the field is `LPUART1_TX_WKUP`"]
#[inline(always)]
pub fn is_lpuart1_tx_wkup(&self) -> bool {
*self == SYNC_IDR::LPUART1_TX_WKUP
}
#[doc = "Checks if the value of the field is `LPTIM2_OUT`"]
#[inline(always)]
pub fn is_lptim2_out(&self) -> bool {
*self == SYNC_IDR::LPTIM2_OUT
}
#[doc = "Checks if the value of the field is `LPTIM3_OUT`"]
#[inline(always)]
pub fn is_lptim3_out(&self) -> bool {
*self == SYNC_IDR::LPTIM3_OUT
}
#[doc = "Checks if the value of the field is `I2C4_WKUP`"]
#[inline(always)]
pub fn is_i2c4_wkup(&self) -> bool {
*self == SYNC_IDR::I2C4_WKUP
}
#[doc = "Checks if the value of the field is `SPI6_WKUP`"]
#[inline(always)]
pub fn is_spi6_wkup(&self) -> bool {
*self == SYNC_IDR::SPI6_WKUP
}
#[doc = "Checks if the value of the field is `COMP1_OUT`"]
#[inline(always)]
pub fn is_comp1_out(&self) -> bool {
*self == SYNC_IDR::COMP1_OUT
}
#[doc = "Checks if the value of the field is `RTC_WKUP`"]
#[inline(always)]
pub fn is_rtc_wkup(&self) -> bool {
*self == SYNC_IDR::RTC_WKUP
}
#[doc = "Checks if the value of the field is `SYSCFG_EXTI0_MUX`"]
#[inline(always)]
pub fn is_syscfg_exti0_mux(&self) -> bool {
*self == SYNC_IDR::SYSCFG_EXTI0_MUX
}
#[doc = "Checks if the value of the field is `SYSCFG_EXTI2_MUX`"]
#[inline(always)]
pub fn is_syscfg_exti2_mux(&self) -> bool {
*self == SYNC_IDR::SYSCFG_EXTI2_MUX
}
}
#[doc = "Values that can be written to the field `SYNC_ID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYNC_IDW {
#[doc = "Signal `dmamux2_evt0` selected as synchronization input"]
DMAMUX2_EVT0,
#[doc = "Signal `dmamux2_evt1` selected as synchronization input"]
DMAMUX2_EVT1,
#[doc = "Signal `dmamux2_evt2` selected as synchronization input"]
DMAMUX2_EVT2,
#[doc = "Signal `dmamux2_evt3` selected as synchronization input"]
DMAMUX2_EVT3,
#[doc = "Signal `dmamux2_evt4` selected as synchronization input"]
DMAMUX2_EVT4,
#[doc = "Signal `dmamux2_evt5` selected as synchronization input"]
DMAMUX2_EVT5,
#[doc = "Signal `lpuart1_rx_wkup` selected as synchronization input"]
LPUART1_RX_WKUP,
#[doc = "Signal `lpuart1_tx_wkup` selected as synchronization input"]
LPUART1_TX_WKUP,
#[doc = "Signal `lptim2_out` selected as synchronization input"]
LPTIM2_OUT,
#[doc = "Signal `lptim3_out` selected as synchronization input"]
LPTIM3_OUT,
#[doc = "Signal `i2c4_wkup` selected as synchronization input"]
I2C4_WKUP,
#[doc = "Signal `spi6_wkup` selected as synchronization input"]
SPI6_WKUP,
#[doc = "Signal `comp1_out` selected as synchronization input"]
COMP1_OUT,
#[doc = "Signal `rtc_wkup` selected as synchronization input"]
RTC_WKUP,
#[doc = "Signal `syscfg_exti0_mux` selected as synchronization input"]
SYSCFG_EXTI0_MUX,
#[doc = "Signal `syscfg_exti2_mux` selected as synchronization input"]
SYSCFG_EXTI2_MUX,
}
impl SYNC_IDW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SYNC_IDW::DMAMUX2_EVT0 => 0,
SYNC_IDW::DMAMUX2_EVT1 => 1,
SYNC_IDW::DMAMUX2_EVT2 => 2,
SYNC_IDW::DMAMUX2_EVT3 => 3,
SYNC_IDW::DMAMUX2_EVT4 => 4,
SYNC_IDW::DMAMUX2_EVT5 => 5,
SYNC_IDW::LPUART1_RX_WKUP => 6,
SYNC_IDW::LPUART1_TX_WKUP => 7,
SYNC_IDW::LPTIM2_OUT => 8,
SYNC_IDW::LPTIM3_OUT => 9,
SYNC_IDW::I2C4_WKUP => 10,
SYNC_IDW::SPI6_WKUP => 11,
SYNC_IDW::COMP1_OUT => 12,
SYNC_IDW::RTC_WKUP => 13,
SYNC_IDW::SYSCFG_EXTI0_MUX => 14,
SYNC_IDW::SYSCFG_EXTI2_MUX => 15,
}
}
}
#[doc = r"Proxy"]
pub struct _SYNC_IDW<'a> {
w: &'a mut W,
}
impl<'a> _SYNC_IDW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SYNC_IDW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Signal `dmamux2_evt0` selected as synchronization input"]
#[inline(always)]
pub fn dmamux2_evt0(self) -> &'a mut W {
self.variant(SYNC_IDW::DMAMUX2_EVT0)
}
#[doc = "Signal `dmamux2_evt1` selected as synchronization input"]
#[inline(always)]
pub fn dmamux2_evt1(self) -> &'a mut W {
self.variant(SYNC_IDW::DMAMUX2_EVT1)
}
#[doc = "Signal `dmamux2_evt2` selected as synchronization input"]
#[inline(always)]
pub fn dmamux2_evt2(self) -> &'a mut W {
self.variant(SYNC_IDW::DMAMUX2_EVT2)
}
#[doc = "Signal `dmamux2_evt3` selected as synchronization input"]
#[inline(always)]
pub fn dmamux2_evt3(self) -> &'a mut W {
self.variant(SYNC_IDW::DMAMUX2_EVT3)
}
#[doc = "Signal `dmamux2_evt4` selected as synchronization input"]
#[inline(always)]
pub fn dmamux2_evt4(self) -> &'a mut W {
self.variant(SYNC_IDW::DMAMUX2_EVT4)
}
#[doc = "Signal `dmamux2_evt5` selected as synchronization input"]
#[inline(always)]
pub fn dmamux2_evt5(self) -> &'a mut W {
self.variant(SYNC_IDW::DMAMUX2_EVT5)
}
#[doc = "Signal `lpuart1_rx_wkup` selected as synchronization input"]
#[inline(always)]
pub fn lpuart1_rx_wkup(self) -> &'a mut W {
self.variant(SYNC_IDW::LPUART1_RX_WKUP)
}
#[doc = "Signal `lpuart1_tx_wkup` selected as synchronization input"]
#[inline(always)]
pub fn lpuart1_tx_wkup(self) -> &'a mut W {
self.variant(SYNC_IDW::LPUART1_TX_WKUP)
}
#[doc = "Signal `lptim2_out` selected as synchronization input"]
#[inline(always)]
pub fn lptim2_out(self) -> &'a mut W {
self.variant(SYNC_IDW::LPTIM2_OUT)
}
#[doc = "Signal `lptim3_out` selected as synchronization input"]
#[inline(always)]
pub fn lptim3_out(self) -> &'a mut W {
self.variant(SYNC_IDW::LPTIM3_OUT)
}
#[doc = "Signal `i2c4_wkup` selected as synchronization input"]
#[inline(always)]
pub fn i2c4_wkup(self) -> &'a mut W {
self.variant(SYNC_IDW::I2C4_WKUP)
}
#[doc = "Signal `spi6_wkup` selected as synchronization input"]
#[inline(always)]
pub fn spi6_wkup(self) -> &'a mut W {
self.variant(SYNC_IDW::SPI6_WKUP)
}
#[doc = "Signal `comp1_out` selected as synchronization input"]
#[inline(always)]
pub fn comp1_out(self) -> &'a mut W {
self.variant(SYNC_IDW::COMP1_OUT)
}
#[doc = "Signal `rtc_wkup` selected as synchronization input"]
#[inline(always)]
pub fn rtc_wkup(self) -> &'a mut W {
self.variant(SYNC_IDW::RTC_WKUP)
}
#[doc = "Signal `syscfg_exti0_mux` selected as synchronization input"]
#[inline(always)]
pub fn syscfg_exti0_mux(self) -> &'a mut W {
self.variant(SYNC_IDW::SYSCFG_EXTI0_MUX)
}
#[doc = "Signal `syscfg_exti2_mux` selected as synchronization input"]
#[inline(always)]
pub fn syscfg_exti2_mux(self) -> &'a mut W {
self.variant(SYNC_IDW::SYSCFG_EXTI2_MUX)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 24);
self.w.bits |= ((value as u32) & 0x1f) << 24;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Input DMA request line selected"]
#[inline(always)]
pub fn dmareq_id(&self) -> DMAREQ_IDR {
DMAREQ_IDR::_from(((self.bits >> 0) & 0xff) as u8)
}
#[doc = "Bit 8 - Interrupt enable at synchronization event overrun"]
#[inline(always)]
pub fn soie(&self) -> SOIER {
SOIER::_from(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 9 - Event generation enable/disable"]
#[inline(always)]
pub fn ege(&self) -> EGER {
EGER::_from(((self.bits >> 9) & 0x01) != 0)
}
#[doc = "Bit 16 - Synchronous operating mode enable/disable"]
#[inline(always)]
pub fn se(&self) -> SER {
SER::_from(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:"]
#[inline(always)]
pub fn spol(&self) -> SPOLR {
SPOLR::_from(((self.bits >> 17) & 0x03) as u8)
}
#[doc = "Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset."]
#[inline(always)]
pub fn nbreq(&self) -> NBREQR {
let bits = ((self.bits >> 19) & 0x1f) as u8;
NBREQR { bits }
}
#[doc = "Bits 24:28 - Synchronization input selected"]
#[inline(always)]
pub fn sync_id(&self) -> SYNC_IDR {
SYNC_IDR::_from(((self.bits >> 24) & 0x1f) as u8)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Input DMA request line selected"]
#[inline(always)]
pub fn dmareq_id(&mut self) -> _DMAREQ_IDW {
_DMAREQ_IDW { w: self }
}
#[doc = "Bit 8 - Interrupt enable at synchronization event overrun"]
#[inline(always)]
pub fn soie(&mut self) -> _SOIEW {
_SOIEW { w: self }
}
#[doc = "Bit 9 - Event generation enable/disable"]
#[inline(always)]
pub fn ege(&mut self) -> _EGEW {
_EGEW { w: self }
}
#[doc = "Bit 16 - Synchronous operating mode enable/disable"]
#[inline(always)]
pub fn se(&mut self) -> _SEW {
_SEW { w: self }
}
#[doc = "Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:"]
#[inline(always)]
pub fn spol(&mut self) -> _SPOLW {
_SPOLW { w: self }
}
#[doc = "Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset."]
#[inline(always)]
pub fn nbreq(&mut self) -> _NBREQW {
_NBREQW { w: self }
}
#[doc = "Bits 24:28 - Synchronization input selected"]
#[inline(always)]
pub fn sync_id(&mut self) -> _SYNC_IDW {
_SYNC_IDW { w: self }
}
}