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#[doc = r"Value read from the register"] pub struct R { bits: u32, } #[doc = r"Value to write to the register"] pub struct W { bits: u32, } impl super::CR { #[doc = r"Modifies the contents of the register"] #[inline(always)] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set(f(&R { bits }, &mut W { bits }).bits); } #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r"Writes to the register"] #[inline(always)] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { self.register.set( f(&mut W { bits: Self::reset_value(), }) .bits, ); } #[doc = r"Reset value of the register"] #[inline(always)] pub const fn reset_value() -> u32 { 0x2000 } #[doc = r"Writes the reset value to the register"] #[inline(always)] pub fn reset(&self) { self.register.set(Self::reset_value()) } } #[doc = r"Value of the field"] pub struct SYNCOKIER { bits: bool, } impl SYNCOKIER { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Proxy"] pub struct _SYNCOKIEW<'a> { w: &'a mut W, } impl<'a> _SYNCOKIEW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits &= !(0x01 << 0); self.w.bits |= ((value as u32) & 0x01) << 0; self.w } } #[doc = r"Value of the field"] pub struct SYNCWARNIER { bits: bool, } impl SYNCWARNIER { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Proxy"] pub struct _SYNCWARNIEW<'a> { w: &'a mut W, } impl<'a> _SYNCWARNIEW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits &= !(0x01 << 1); self.w.bits |= ((value as u32) & 0x01) << 1; self.w } } #[doc = r"Value of the field"] pub struct ERRIER { bits: bool, } impl ERRIER { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Proxy"] pub struct _ERRIEW<'a> { w: &'a mut W, } impl<'a> _ERRIEW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits &= !(0x01 << 2); self.w.bits |= ((value as u32) & 0x01) << 2; self.w } } #[doc = r"Value of the field"] pub struct ESYNCIER { bits: bool, } impl ESYNCIER { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Proxy"] pub struct _ESYNCIEW<'a> { w: &'a mut W, } impl<'a> _ESYNCIEW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits &= !(0x01 << 3); self.w.bits |= ((value as u32) & 0x01) << 3; self.w } } #[doc = r"Value of the field"] pub struct CENR { bits: bool, } impl CENR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Proxy"] pub struct _CENW<'a> { w: &'a mut W, } impl<'a> _CENW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits &= !(0x01 << 5); self.w.bits |= ((value as u32) & 0x01) << 5; self.w } } #[doc = r"Value of the field"] pub struct AUTOTRIMENR { bits: bool, } impl AUTOTRIMENR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Proxy"] pub struct _AUTOTRIMENW<'a> { w: &'a mut W, } impl<'a> _AUTOTRIMENW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits &= !(0x01 << 6); self.w.bits |= ((value as u32) & 0x01) << 6; self.w } } #[doc = r"Value of the field"] pub struct SWSYNCR { bits: bool, } impl SWSYNCR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { self.bits } #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r"Value of the field"] pub struct TRIMR { bits: u8, } impl TRIMR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _TRIMW<'a> { w: &'a mut W, } impl<'a> _TRIMW<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x3f << 8); self.w.bits |= ((value as u32) & 0x3f) << 8; self.w } } impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bit 0 - SYNC event OK interrupt enable"] #[inline(always)] pub fn syncokie(&self) -> SYNCOKIER { let bits = ((self.bits >> 0) & 0x01) != 0; SYNCOKIER { bits } } #[doc = "Bit 1 - SYNC warning interrupt enable"] #[inline(always)] pub fn syncwarnie(&self) -> SYNCWARNIER { let bits = ((self.bits >> 1) & 0x01) != 0; SYNCWARNIER { bits } } #[doc = "Bit 2 - Synchronization or trimming error interrupt enable"] #[inline(always)] pub fn errie(&self) -> ERRIER { let bits = ((self.bits >> 2) & 0x01) != 0; ERRIER { bits } } #[doc = "Bit 3 - Expected SYNC interrupt enable"] #[inline(always)] pub fn esyncie(&self) -> ESYNCIER { let bits = ((self.bits >> 3) & 0x01) != 0; ESYNCIER { bits } } #[doc = "Bit 5 - Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified."] #[inline(always)] pub fn cen(&self) -> CENR { let bits = ((self.bits >> 5) & 0x01) != 0; CENR { bits } } #[doc = "Bit 6 - Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details."] #[inline(always)] pub fn autotrimen(&self) -> AUTOTRIMENR { let bits = ((self.bits >> 6) & 0x01) != 0; AUTOTRIMENR { bits } } #[doc = "Bit 7 - Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware."] #[inline(always)] pub fn swsync(&self) -> SWSYNCR { let bits = ((self.bits >> 7) & 0x01) != 0; SWSYNCR { bits } } #[doc = "Bits 8:13 - HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only."] #[inline(always)] pub fn trim(&self) -> TRIMR { let bits = ((self.bits >> 8) & 0x3f) as u8; TRIMR { bits } } } impl W { #[doc = r"Writes raw bits to the register"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bit 0 - SYNC event OK interrupt enable"] #[inline(always)] pub fn syncokie(&mut self) -> _SYNCOKIEW { _SYNCOKIEW { w: self } } #[doc = "Bit 1 - SYNC warning interrupt enable"] #[inline(always)] pub fn syncwarnie(&mut self) -> _SYNCWARNIEW { _SYNCWARNIEW { w: self } } #[doc = "Bit 2 - Synchronization or trimming error interrupt enable"] #[inline(always)] pub fn errie(&mut self) -> _ERRIEW { _ERRIEW { w: self } } #[doc = "Bit 3 - Expected SYNC interrupt enable"] #[inline(always)] pub fn esyncie(&mut self) -> _ESYNCIEW { _ESYNCIEW { w: self } } #[doc = "Bit 5 - Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified."] #[inline(always)] pub fn cen(&mut self) -> _CENW { _CENW { w: self } } #[doc = "Bit 6 - Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details."] #[inline(always)] pub fn autotrimen(&mut self) -> _AUTOTRIMENW { _AUTOTRIMENW { w: self } } #[doc = "Bits 8:13 - HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only."] #[inline(always)] pub fn trim(&mut self) -> _TRIMW { _TRIMW { w: self } } }