Expand description

CPU2 EXTI interrupt mask register

Re-exports

pub use MR64_A as MR65_A;
pub use MR64_A as MR66_A;
pub use MR64_A as MR67_A;
pub use MR64_A as MR68_A;
pub use MR64_A as MR69_A;
pub use MR64_A as MR70_A;
pub use MR64_A as MR71_A;
pub use MR64_A as MR72_A;
pub use MR64_A as MR73_A;
pub use MR64_A as MR74_A;
pub use MR64_A as MR75_A;
pub use MR64_A as MR76_A;
pub use MR64_A as MR77_A;
pub use MR64_A as MR78_A;
pub use MR64_A as MR79_A;
pub use MR64_A as MR80_A;
pub use MR64_A as MR82_A;
pub use MR64_A as MR84_A;
pub use MR64_A as MR85_A;
pub use MR64_A as MR86_A;
pub use MR64_A as MR87_A;
pub use MR64_A as MR88_A;
pub use MR64_R as MR65_R;
pub use MR64_R as MR66_R;
pub use MR64_R as MR67_R;
pub use MR64_R as MR68_R;
pub use MR64_R as MR69_R;
pub use MR64_R as MR70_R;
pub use MR64_R as MR71_R;
pub use MR64_R as MR72_R;
pub use MR64_R as MR73_R;
pub use MR64_R as MR74_R;
pub use MR64_R as MR75_R;
pub use MR64_R as MR76_R;
pub use MR64_R as MR77_R;
pub use MR64_R as MR78_R;
pub use MR64_R as MR79_R;
pub use MR64_R as MR80_R;
pub use MR64_R as MR82_R;
pub use MR64_R as MR84_R;
pub use MR64_R as MR85_R;
pub use MR64_R as MR86_R;
pub use MR64_R as MR87_R;
pub use MR64_R as MR88_R;
pub use MR64_W as MR65_W;
pub use MR64_W as MR66_W;
pub use MR64_W as MR67_W;
pub use MR64_W as MR68_W;
pub use MR64_W as MR69_W;
pub use MR64_W as MR70_W;
pub use MR64_W as MR71_W;
pub use MR64_W as MR72_W;
pub use MR64_W as MR73_W;
pub use MR64_W as MR74_W;
pub use MR64_W as MR75_W;
pub use MR64_W as MR76_W;
pub use MR64_W as MR77_W;
pub use MR64_W as MR78_W;
pub use MR64_W as MR79_W;
pub use MR64_W as MR80_W;
pub use MR64_W as MR82_W;
pub use MR64_W as MR84_W;
pub use MR64_W as MR85_W;
pub use MR64_W as MR86_W;
pub use MR64_W as MR87_W;
pub use MR64_W as MR88_W;

Structs

CPU2 EXTI interrupt mask register

Register C2IMR3 reader

Register C2IMR3 writer

Enums

CPU2 interrupt Mask on Direct Event input x+64

Type Definitions

Field MR64 reader - CPU2 interrupt Mask on Direct Event input x+64

Field MR64 writer - CPU2 interrupt Mask on Direct Event input x+64