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#[doc = "Reader of register FRCR"] pub type R = crate::R<u32, super::FRCR>; #[doc = "Writer for register FRCR"] pub type W = crate::W<u32, super::FRCR>; #[doc = "Register FRCR `reset()`'s with value 0x07"] impl crate::ResetValue for super::FRCR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x07 } } #[doc = "Reader of field `FRL`"] pub type FRL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `FRL`"] pub struct FRL_W<'a> { w: &'a mut W, } impl<'a> FRL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); self.w } } #[doc = "Reader of field `FSALL`"] pub type FSALL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `FSALL`"] pub struct FSALL_W<'a> { w: &'a mut W, } impl<'a> FSALL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8); self.w } } #[doc = "Reader of field `FSDEF`"] pub type FSDEF_R = crate::R<bool, bool>; #[doc = "Write proxy for field `FSDEF`"] pub struct FSDEF_W<'a> { w: &'a mut W, } impl<'a> FSDEF_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FSPOL_A { #[doc = "0: FS is active low (falling edge)"] FALLINGEDGE = 0, #[doc = "1: FS is active high (rising edge)"] RISINGEDGE = 1, } impl From<FSPOL_A> for bool { #[inline(always)] fn from(variant: FSPOL_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `FSPOL`"] pub type FSPOL_R = crate::R<bool, FSPOL_A>; impl FSPOL_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> FSPOL_A { match self.bits { false => FSPOL_A::FALLINGEDGE, true => FSPOL_A::RISINGEDGE, } } #[doc = "Checks if the value of the field is `FALLINGEDGE`"] #[inline(always)] pub fn is_falling_edge(&self) -> bool { *self == FSPOL_A::FALLINGEDGE } #[doc = "Checks if the value of the field is `RISINGEDGE`"] #[inline(always)] pub fn is_rising_edge(&self) -> bool { *self == FSPOL_A::RISINGEDGE } } #[doc = "Write proxy for field `FSPOL`"] pub struct FSPOL_W<'a> { w: &'a mut W, } impl<'a> FSPOL_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: FSPOL_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "FS is active low (falling edge)"] #[inline(always)] pub fn falling_edge(self) -> &'a mut W { self.variant(FSPOL_A::FALLINGEDGE) } #[doc = "FS is active high (rising edge)"] #[inline(always)] pub fn rising_edge(self) -> &'a mut W { self.variant(FSPOL_A::RISINGEDGE) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); self.w } } #[doc = "Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FSOFF_A { #[doc = "0: FS is asserted on the first bit of the slot 0"] ONFIRST = 0, #[doc = "1: FS is asserted one bit before the first bit of the slot 0"] BEFOREFIRST = 1, } impl From<FSOFF_A> for bool { #[inline(always)] fn from(variant: FSOFF_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `FSOFF`"] pub type FSOFF_R = crate::R<bool, FSOFF_A>; impl FSOFF_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> FSOFF_A { match self.bits { false => FSOFF_A::ONFIRST, true => FSOFF_A::BEFOREFIRST, } } #[doc = "Checks if the value of the field is `ONFIRST`"] #[inline(always)] pub fn is_on_first(&self) -> bool { *self == FSOFF_A::ONFIRST } #[doc = "Checks if the value of the field is `BEFOREFIRST`"] #[inline(always)] pub fn is_before_first(&self) -> bool { *self == FSOFF_A::BEFOREFIRST } } #[doc = "Write proxy for field `FSOFF`"] pub struct FSOFF_W<'a> { w: &'a mut W, } impl<'a> FSOFF_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: FSOFF_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "FS is asserted on the first bit of the slot 0"] #[inline(always)] pub fn on_first(self) -> &'a mut W { self.variant(FSOFF_A::ONFIRST) } #[doc = "FS is asserted one bit before the first bit of the slot 0"] #[inline(always)] pub fn before_first(self) -> &'a mut W { self.variant(FSOFF_A::BEFOREFIRST) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); self.w } } impl R { #[doc = "Bits 0:7 - Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL\\[7:0\\] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT\\[4:0\\] of SAI_xSLOTR register (NBSLOT\\[3:0\\] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration."] #[inline(always)] pub fn frl(&self) -> FRL_R { FRL_R::new((self.bits & 0xff) as u8) } #[doc = "Bits 8:14 - Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL\\[6:0\\] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled."] #[inline(always)] pub fn fsall(&self) -> FSALL_R { FSALL_R::new(((self.bits >> 8) & 0x7f) as u8) } #[doc = "Bit 16 - Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled."] #[inline(always)] pub fn fsdef(&self) -> FSDEF_R { FSDEF_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bit 17 - Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled."] #[inline(always)] pub fn fspol(&self) -> FSPOL_R { FSPOL_R::new(((self.bits >> 17) & 0x01) != 0) } #[doc = "Bit 18 - Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled."] #[inline(always)] pub fn fsoff(&self) -> FSOFF_R { FSOFF_R::new(((self.bits >> 18) & 0x01) != 0) } } impl W { #[doc = "Bits 0:7 - Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL\\[7:0\\] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT\\[4:0\\] of SAI_xSLOTR register (NBSLOT\\[3:0\\] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration."] #[inline(always)] pub fn frl(&mut self) -> FRL_W { FRL_W { w: self } } #[doc = "Bits 8:14 - Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL\\[6:0\\] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled."] #[inline(always)] pub fn fsall(&mut self) -> FSALL_W { FSALL_W { w: self } } #[doc = "Bit 16 - Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled."] #[inline(always)] pub fn fsdef(&mut self) -> FSDEF_W { FSDEF_W { w: self } } #[doc = "Bit 17 - Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled."] #[inline(always)] pub fn fspol(&mut self) -> FSPOL_W { FSPOL_W { w: self } } #[doc = "Bit 18 - Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled."] #[inline(always)] pub fn fsoff(&mut self) -> FSOFF_W { FSOFF_W { w: self } } }