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#[doc = "Reader of register CICR"] pub type R = crate::R<u32, super::CICR>; #[doc = "Writer for register CICR"] pub type W = crate::W<u32, super::CICR>; #[doc = "Register CICR `reset()`'s with value 0"] impl crate::ResetValue for super::CICR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "LSI ready Interrupt Clear\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum LSIRDYC_A { #[doc = "1: Clear interrupt flag"] CLEAR = 1, } impl From<LSIRDYC_A> for bool { #[inline(always)] fn from(variant: LSIRDYC_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `LSIRDYC`"] pub type LSIRDYC_R = crate::R<bool, LSIRDYC_A>; impl LSIRDYC_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<bool, LSIRDYC_A> { use crate::Variant::*; match self.bits { true => Val(LSIRDYC_A::CLEAR), i => Res(i), } } #[doc = "Checks if the value of the field is `CLEAR`"] #[inline(always)] pub fn is_clear(&self) -> bool { *self == LSIRDYC_A::CLEAR } } #[doc = "Write proxy for field `LSIRDYC`"] pub struct LSIRDYC_W<'a> { w: &'a mut W, } impl<'a> LSIRDYC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: LSIRDYC_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clear interrupt flag"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(LSIRDYC_A::CLEAR) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = "LSE ready Interrupt Clear"] pub type LSERDYC_A = LSIRDYC_A; #[doc = "Reader of field `LSERDYC`"] pub type LSERDYC_R = crate::R<bool, LSIRDYC_A>; #[doc = "Write proxy for field `LSERDYC`"] pub struct LSERDYC_W<'a> { w: &'a mut W, } impl<'a> LSERDYC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: LSERDYC_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clear interrupt flag"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(LSIRDYC_A::CLEAR) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "HSI ready Interrupt Clear"] pub type HSIRDYC_A = LSIRDYC_A; #[doc = "Reader of field `HSIRDYC`"] pub type HSIRDYC_R = crate::R<bool, LSIRDYC_A>; #[doc = "Write proxy for field `HSIRDYC`"] pub struct HSIRDYC_W<'a> { w: &'a mut W, } impl<'a> HSIRDYC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: HSIRDYC_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clear interrupt flag"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(LSIRDYC_A::CLEAR) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = "HSE ready Interrupt Clear"] pub type HSERDYC_A = LSIRDYC_A; #[doc = "Reader of field `HSERDYC`"] pub type HSERDYC_R = crate::R<bool, LSIRDYC_A>; #[doc = "Write proxy for field `HSERDYC`"] pub struct HSERDYC_W<'a> { w: &'a mut W, } impl<'a> HSERDYC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: HSERDYC_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clear interrupt flag"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(LSIRDYC_A::CLEAR) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `HSE_ready_Interrupt_Clear`"] pub type HSE_READY_INTERRUPT_CLEAR_R = crate::R<bool, bool>; #[doc = "Write proxy for field `HSE_ready_Interrupt_Clear`"] pub struct HSE_READY_INTERRUPT_CLEAR_W<'a> { w: &'a mut W, } impl<'a> HSE_READY_INTERRUPT_CLEAR_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); self.w } } #[doc = "RC48 ready Interrupt Clear"] pub type HSI48RDYC_A = LSIRDYC_A; #[doc = "Reader of field `HSI48RDYC`"] pub type HSI48RDYC_R = crate::R<bool, LSIRDYC_A>; #[doc = "Write proxy for field `HSI48RDYC`"] pub struct HSI48RDYC_W<'a> { w: &'a mut W, } impl<'a> HSI48RDYC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: HSI48RDYC_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clear interrupt flag"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(LSIRDYC_A::CLEAR) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); self.w } } #[doc = "PLL1 ready Interrupt Clear"] pub type PLL1RDYC_A = LSIRDYC_A; #[doc = "Reader of field `PLL1RDYC`"] pub type PLL1RDYC_R = crate::R<bool, LSIRDYC_A>; #[doc = "Write proxy for field `PLL1RDYC`"] pub struct PLL1RDYC_W<'a> { w: &'a mut W, } impl<'a> PLL1RDYC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: PLL1RDYC_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clear interrupt flag"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(LSIRDYC_A::CLEAR) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); self.w } } #[doc = "PLL2 ready Interrupt Clear"] pub type PLL2RDYC_A = LSIRDYC_A; #[doc = "Reader of field `PLL2RDYC`"] pub type PLL2RDYC_R = crate::R<bool, LSIRDYC_A>; #[doc = "Write proxy for field `PLL2RDYC`"] pub struct PLL2RDYC_W<'a> { w: &'a mut W, } impl<'a> PLL2RDYC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: PLL2RDYC_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clear interrupt flag"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(LSIRDYC_A::CLEAR) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); self.w } } #[doc = "PLL3 ready Interrupt Clear"] pub type PLL3RDYC_A = LSIRDYC_A; #[doc = "Reader of field `PLL3RDYC`"] pub type PLL3RDYC_R = crate::R<bool, LSIRDYC_A>; #[doc = "Write proxy for field `PLL3RDYC`"] pub struct PLL3RDYC_W<'a> { w: &'a mut W, } impl<'a> PLL3RDYC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: PLL3RDYC_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clear interrupt flag"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(LSIRDYC_A::CLEAR) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "LSE clock security system Interrupt Clear"] pub type LSECSSC_A = LSIRDYC_A; #[doc = "Reader of field `LSECSSC`"] pub type LSECSSC_R = crate::R<bool, LSIRDYC_A>; #[doc = "Write proxy for field `LSECSSC`"] pub struct LSECSSC_W<'a> { w: &'a mut W, } impl<'a> LSECSSC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: LSECSSC_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clear interrupt flag"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(LSIRDYC_A::CLEAR) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); self.w } } #[doc = "HSE clock security system Interrupt Clear"] pub type HSECSSC_A = LSIRDYC_A; #[doc = "Reader of field `HSECSSC`"] pub type HSECSSC_R = crate::R<bool, LSIRDYC_A>; #[doc = "Write proxy for field `HSECSSC`"] pub struct HSECSSC_W<'a> { w: &'a mut W, } impl<'a> HSECSSC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: HSECSSC_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clear interrupt flag"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(LSIRDYC_A::CLEAR) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); self.w } } impl R { #[doc = "Bit 0 - LSI ready Interrupt Clear"] #[inline(always)] pub fn lsirdyc(&self) -> LSIRDYC_R { LSIRDYC_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - LSE ready Interrupt Clear"] #[inline(always)] pub fn lserdyc(&self) -> LSERDYC_R { LSERDYC_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 2 - HSI ready Interrupt Clear"] #[inline(always)] pub fn hsirdyc(&self) -> HSIRDYC_R { HSIRDYC_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 3 - HSE ready Interrupt Clear"] #[inline(always)] pub fn hserdyc(&self) -> HSERDYC_R { HSERDYC_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 4 - CSI ready Interrupt Clear"] #[inline(always)] pub fn hse_ready_interrupt_clear(&self) -> HSE_READY_INTERRUPT_CLEAR_R { HSE_READY_INTERRUPT_CLEAR_R::new(((self.bits >> 4) & 0x01) != 0) } #[doc = "Bit 5 - RC48 ready Interrupt Clear"] #[inline(always)] pub fn hsi48rdyc(&self) -> HSI48RDYC_R { HSI48RDYC_R::new(((self.bits >> 5) & 0x01) != 0) } #[doc = "Bit 6 - PLL1 ready Interrupt Clear"] #[inline(always)] pub fn pll1rdyc(&self) -> PLL1RDYC_R { PLL1RDYC_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 7 - PLL2 ready Interrupt Clear"] #[inline(always)] pub fn pll2rdyc(&self) -> PLL2RDYC_R { PLL2RDYC_R::new(((self.bits >> 7) & 0x01) != 0) } #[doc = "Bit 8 - PLL3 ready Interrupt Clear"] #[inline(always)] pub fn pll3rdyc(&self) -> PLL3RDYC_R { PLL3RDYC_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 9 - LSE clock security system Interrupt Clear"] #[inline(always)] pub fn lsecssc(&self) -> LSECSSC_R { LSECSSC_R::new(((self.bits >> 9) & 0x01) != 0) } #[doc = "Bit 10 - HSE clock security system Interrupt Clear"] #[inline(always)] pub fn hsecssc(&self) -> HSECSSC_R { HSECSSC_R::new(((self.bits >> 10) & 0x01) != 0) } } impl W { #[doc = "Bit 0 - LSI ready Interrupt Clear"] #[inline(always)] pub fn lsirdyc(&mut self) -> LSIRDYC_W { LSIRDYC_W { w: self } } #[doc = "Bit 1 - LSE ready Interrupt Clear"] #[inline(always)] pub fn lserdyc(&mut self) -> LSERDYC_W { LSERDYC_W { w: self } } #[doc = "Bit 2 - HSI ready Interrupt Clear"] #[inline(always)] pub fn hsirdyc(&mut self) -> HSIRDYC_W { HSIRDYC_W { w: self } } #[doc = "Bit 3 - HSE ready Interrupt Clear"] #[inline(always)] pub fn hserdyc(&mut self) -> HSERDYC_W { HSERDYC_W { w: self } } #[doc = "Bit 4 - CSI ready Interrupt Clear"] #[inline(always)] pub fn hse_ready_interrupt_clear(&mut self) -> HSE_READY_INTERRUPT_CLEAR_W { HSE_READY_INTERRUPT_CLEAR_W { w: self } } #[doc = "Bit 5 - RC48 ready Interrupt Clear"] #[inline(always)] pub fn hsi48rdyc(&mut self) -> HSI48RDYC_W { HSI48RDYC_W { w: self } } #[doc = "Bit 6 - PLL1 ready Interrupt Clear"] #[inline(always)] pub fn pll1rdyc(&mut self) -> PLL1RDYC_W { PLL1RDYC_W { w: self } } #[doc = "Bit 7 - PLL2 ready Interrupt Clear"] #[inline(always)] pub fn pll2rdyc(&mut self) -> PLL2RDYC_W { PLL2RDYC_W { w: self } } #[doc = "Bit 8 - PLL3 ready Interrupt Clear"] #[inline(always)] pub fn pll3rdyc(&mut self) -> PLL3RDYC_W { PLL3RDYC_W { w: self } } #[doc = "Bit 9 - LSE clock security system Interrupt Clear"] #[inline(always)] pub fn lsecssc(&mut self) -> LSECSSC_W { LSECSSC_W { w: self } } #[doc = "Bit 10 - HSE clock security system Interrupt Clear"] #[inline(always)] pub fn hsecssc(&mut self) -> HSECSSC_W { HSECSSC_W { w: self } } }