1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
#[doc = "Reader of register OAR1"] pub type R = crate::R<u32, super::OAR1>; #[doc = "Writer for register OAR1"] pub type W = crate::W<u32, super::OAR1>; #[doc = "Register OAR1 `reset()`'s with value 0"] impl crate::ResetValue for super::OAR1 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `OA1`"] pub type OA1_R = crate::R<u16, u16>; #[doc = "Write proxy for field `OA1`"] pub struct OA1_W<'a> { w: &'a mut W, } impl<'a> OA1_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u16) -> &'a mut W { self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff); self.w } } #[doc = "Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OA1MODE_A { #[doc = "0: Own address 1 is a 7-bit address"] BIT7 = 0, #[doc = "1: Own address 1 is a 10-bit address"] BIT10 = 1, } impl From<OA1MODE_A> for bool { #[inline(always)] fn from(variant: OA1MODE_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `OA1MODE`"] pub type OA1MODE_R = crate::R<bool, OA1MODE_A>; impl OA1MODE_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> OA1MODE_A { match self.bits { false => OA1MODE_A::BIT7, true => OA1MODE_A::BIT10, } } #[doc = "Checks if the value of the field is `BIT7`"] #[inline(always)] pub fn is_bit7(&self) -> bool { *self == OA1MODE_A::BIT7 } #[doc = "Checks if the value of the field is `BIT10`"] #[inline(always)] pub fn is_bit10(&self) -> bool { *self == OA1MODE_A::BIT10 } } #[doc = "Write proxy for field `OA1MODE`"] pub struct OA1MODE_W<'a> { w: &'a mut W, } impl<'a> OA1MODE_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: OA1MODE_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Own address 1 is a 7-bit address"] #[inline(always)] pub fn bit7(self) -> &'a mut W { self.variant(OA1MODE_A::BIT7) } #[doc = "Own address 1 is a 10-bit address"] #[inline(always)] pub fn bit10(self) -> &'a mut W { self.variant(OA1MODE_A::BIT10) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); self.w } } #[doc = "Own Address 1 enable\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OA1EN_A { #[doc = "0: Own address 1 disabled. The received slave address OA1 is NACKed"] DISABLED = 0, #[doc = "1: Own address 1 enabled. The received slave address OA1 is ACKed"] ENABLED = 1, } impl From<OA1EN_A> for bool { #[inline(always)] fn from(variant: OA1EN_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `OA1EN`"] pub type OA1EN_R = crate::R<bool, OA1EN_A>; impl OA1EN_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> OA1EN_A { match self.bits { false => OA1EN_A::DISABLED, true => OA1EN_A::ENABLED, } } #[doc = "Checks if the value of the field is `DISABLED`"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == OA1EN_A::DISABLED } #[doc = "Checks if the value of the field is `ENABLED`"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == OA1EN_A::ENABLED } } #[doc = "Write proxy for field `OA1EN`"] pub struct OA1EN_W<'a> { w: &'a mut W, } impl<'a> OA1EN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: OA1EN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Own address 1 disabled. The received slave address OA1 is NACKed"] #[inline(always)] pub fn disabled(self) -> &'a mut W { self.variant(OA1EN_A::DISABLED) } #[doc = "Own address 1 enabled. The received slave address OA1 is ACKed"] #[inline(always)] pub fn enabled(self) -> &'a mut W { self.variant(OA1EN_A::ENABLED) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } impl R { #[doc = "Bits 0:9 - Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1\\[7:1\\]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1\\[0\\]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0."] #[inline(always)] pub fn oa1(&self) -> OA1_R { OA1_R::new((self.bits & 0x03ff) as u16) } #[doc = "Bit 10 - Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0."] #[inline(always)] pub fn oa1mode(&self) -> OA1MODE_R { OA1MODE_R::new(((self.bits >> 10) & 0x01) != 0) } #[doc = "Bit 15 - Own Address 1 enable"] #[inline(always)] pub fn oa1en(&self) -> OA1EN_R { OA1EN_R::new(((self.bits >> 15) & 0x01) != 0) } } impl W { #[doc = "Bits 0:9 - Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1\\[7:1\\]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1\\[0\\]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0."] #[inline(always)] pub fn oa1(&mut self) -> OA1_W { OA1_W { w: self } } #[doc = "Bit 10 - Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0."] #[inline(always)] pub fn oa1mode(&mut self) -> OA1MODE_W { OA1MODE_W { w: self } } #[doc = "Bit 15 - Own Address 1 enable"] #[inline(always)] pub fn oa1en(&mut self) -> OA1EN_W { OA1EN_W { w: self } } }