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#[doc = "Reader of register SDCMR"] pub type R = crate::R<u32, super::SDCMR>; #[doc = "Writer for register SDCMR"] pub type W = crate::W<u32, super::SDCMR>; #[doc = "Register SDCMR `reset()`'s with value 0"] impl crate::ResetValue for super::SDCMR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `MODE`"] pub type MODE_R = crate::R<u8, u8>; #[doc = "Write proxy for field `MODE`"] pub struct MODE_W<'a> { w: &'a mut W, } impl<'a> MODE_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); self.w } } #[doc = "Reader of field `CTB2`"] pub type CTB2_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CTB2`"] pub struct CTB2_W<'a> { w: &'a mut W, } impl<'a> CTB2_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `CTB1`"] pub type CTB1_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CTB1`"] pub struct CTB1_W<'a> { w: &'a mut W, } impl<'a> CTB1_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); self.w } } #[doc = "Reader of field `NRFS`"] pub type NRFS_R = crate::R<u8, u8>; #[doc = "Write proxy for field `NRFS`"] pub struct NRFS_W<'a> { w: &'a mut W, } impl<'a> NRFS_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 5)) | (((value as u32) & 0x0f) << 5); self.w } } #[doc = "Reader of field `MRD`"] pub type MRD_R = crate::R<u16, u16>; #[doc = "Write proxy for field `MRD`"] pub struct MRD_W<'a> { w: &'a mut W, } impl<'a> MRD_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u16) -> &'a mut W { self.w.bits = (self.w.bits & !(0x3fff << 9)) | (((value as u32) & 0x3fff) << 9); self.w } } impl R { #[doc = "Bits 0:2 - Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0."] #[inline(always)] pub fn mode(&self) -> MODE_R { MODE_R::new((self.bits & 0x07) as u8) } #[doc = "Bit 3 - Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not."] #[inline(always)] pub fn ctb2(&self) -> CTB2_R { CTB2_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 4 - Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not."] #[inline(always)] pub fn ctb1(&self) -> CTB1_R { CTB1_R::new(((self.bits >> 4) & 0x01) != 0) } #[doc = "Bits 5:8 - Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. ...."] #[inline(always)] pub fn nrfs(&self) -> NRFS_R { NRFS_R::new(((self.bits >> 5) & 0x0f) as u8) } #[doc = "Bits 9:22 - Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD\\[13:0\\] bits are also used to program the extended mode register for mobile SDRAM."] #[inline(always)] pub fn mrd(&self) -> MRD_R { MRD_R::new(((self.bits >> 9) & 0x3fff) as u16) } } impl W { #[doc = "Bits 0:2 - Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0."] #[inline(always)] pub fn mode(&mut self) -> MODE_W { MODE_W { w: self } } #[doc = "Bit 3 - Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not."] #[inline(always)] pub fn ctb2(&mut self) -> CTB2_W { CTB2_W { w: self } } #[doc = "Bit 4 - Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not."] #[inline(always)] pub fn ctb1(&mut self) -> CTB1_W { CTB1_W { w: self } } #[doc = "Bits 5:8 - Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. ...."] #[inline(always)] pub fn nrfs(&mut self) -> NRFS_W { NRFS_W { w: self } } #[doc = "Bits 9:22 - Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD\\[13:0\\] bits are also used to program the extended mode register for mobile SDRAM."] #[inline(always)] pub fn mrd(&mut self) -> MRD_W { MRD_W { w: self } } }