SEC_ETH

stm32h5_staging::stm32h573

Struct SEC_ETH 

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pub struct SEC_ETH { /* private fields */ }
Expand description

Ethernet media access control

Implementations§

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impl SEC_ETH

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pub const PTR: *const RegisterBlock = {0x50028000 as *const stm32h573::eth::RegisterBlock}

Pointer to the register block

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pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

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pub unsafe fn steal() -> Self

Steal an instance of this peripheral

§Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>§

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pub fn maccr(&self) -> &MACCR

0x00 - Operating mode configuration register

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pub fn macecr(&self) -> &MACECR

0x04 - Extended operating mode configuration register

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pub fn macpfr(&self) -> &MACPFR

0x08 - Packet filtering control register

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pub fn macwtr(&self) -> &MACWTR

0x0c - Watchdog timeout register

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pub fn macht0r(&self) -> &MACHT0R

0x10 - Hash Table 0 register

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pub fn macht1r(&self) -> &MACHT1R

0x14 - Hash Table 1 register

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pub fn macvtr(&self) -> &MACVTR

0x50 - VLAN tag register

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pub fn macvhtr(&self) -> &MACVHTR

0x58 - VLAN Hash table register

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pub fn macvir(&self) -> &MACVIR

0x60 - VLAN inclusion register

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pub fn macivir(&self) -> &MACIVIR

0x64 - Inner VLAN inclusion register

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pub fn macqtxfcr(&self) -> &MACQTXFCR

0x70 - Tx Queue flow control register

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pub fn macrxfcr(&self) -> &MACRXFCR

0x90 - Rx flow control register

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pub fn macisr(&self) -> &MACISR

0xb0 - Interrupt status register

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pub fn macier(&self) -> &MACIER

0xb4 - Interrupt enable register

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pub fn macrxtxsr(&self) -> &MACRXTXSR

0xb8 - Rx Tx status register

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pub fn macpcsr(&self) -> &MACPCSR

0xc0 - PMT control status register

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pub fn macrwkpfr(&self) -> &MACRWKPFR

0xc4 - Remote wakeup packet filter register

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pub fn maclcsr(&self) -> &MACLCSR

0xd0 - LPI control and status register

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pub fn macltcr(&self) -> &MACLTCR

0xd4 - LPI timers control register

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pub fn macletr(&self) -> &MACLETR

0xd8 - LPI entry timer register

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pub fn mac1ustcr(&self) -> &MAC1USTCR

0xdc - One-microsecond-tick counter register

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pub fn macvr(&self) -> &MACVR

0x110 - Version register

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pub fn macdr(&self) -> &MACDR

0x114 - Debug register

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pub fn machwf0r(&self) -> &MACHWF0R

0x11c - HW feature 0 register

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pub fn machwf1r(&self) -> &MACHWF1R

0x120 - HW feature 1 register

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pub fn machwf2r(&self) -> &MACHWF2R

0x124 - HW feature 2 register

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pub fn machwf3r(&self) -> &MACHWF3R

0x128 - HW feature 3 register

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pub fn macmdioar(&self) -> &MACMDIOAR

0x200 - MDIO address register

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pub fn macmdiodr(&self) -> &MACMDIODR

0x204 - MDIO data register

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pub fn macarpar(&self) -> &MACARPAR

0x210 - ARP address register

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pub fn maccsrswcr(&self) -> &MACCSRSWCR

0x230 - CSR software control register

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pub fn maca0hr(&self) -> &MACA0HR

0x300 - MAC Address 0 high register

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pub fn maca0lr(&self) -> &MACA0LR

0x304 - MAC Address 0 low register

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pub fn maca1hr(&self) -> &MACA1HR

0x308 - MAC Address 1 high register

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pub fn maca1lr(&self) -> &MACA1LR

0x30c - MAC Address 1 low register

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pub fn maca2hr(&self) -> &MACA2HR

0x310 - MAC Address 2 high register

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pub fn maca2lr(&self) -> &MACA2LR

0x314 - MAC Address 2 low register

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pub fn maca3hr(&self) -> &MACA3HR

0x318 - MAC Address 3 high register

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pub fn maca3lr(&self) -> &MACA3LR

0x31c - MAC Address 3 low register

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pub fn mmc_control(&self) -> &MMC_CONTROL

0x700 - MMC control register

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pub fn mmc_rx_interrupt(&self) -> &MMC_RX_INTERRUPT

0x704 - MMC Rx interrupt register

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pub fn mmc_tx_interrupt(&self) -> &MMC_TX_INTERRUPT

0x708 - MMC Tx interrupt register

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pub fn mmc_rx_interrupt_mask(&self) -> &MMC_RX_INTERRUPT_MASK

0x70c - MMC Rx interrupt mask register

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pub fn mmc_tx_interrupt_mask(&self) -> &MMC_TX_INTERRUPT_MASK

0x710 - MMC Tx interrupt mask register

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pub fn tx_single_collision_good_packets( &self, ) -> &TX_SINGLE_COLLISION_GOOD_PACKETS

0x74c - Tx single collision good packets register

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pub fn tx_multiple_collision_good_packets( &self, ) -> &TX_MULTIPLE_COLLISION_GOOD_PACKETS

0x750 - Tx multiple collision good packets register

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pub fn tx_packet_count_good(&self) -> &TX_PACKET_COUNT_GOOD

0x768 - Tx packet count good register

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pub fn rx_crc_error_packets(&self) -> &RX_CRC_ERROR_PACKETS

0x794 - Rx CRC error packets register

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pub fn rx_alignment_error_packets(&self) -> &RX_ALIGNMENT_ERROR_PACKETS

0x798 - Rx alignment error packets register

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pub fn rx_unicast_packets_good(&self) -> &RX_UNICAST_PACKETS_GOOD

0x7c4 - Rx unicast packets good register

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pub fn tx_lpi_usec_cntr(&self) -> &TX_LPI_USEC_CNTR

0x7ec - Tx LPI microsecond timer register

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pub fn tx_lpi_tran_cntr(&self) -> &TX_LPI_TRAN_CNTR

0x7f0 - Tx LPI transition counter register

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pub fn rx_lpi_usec_cntr(&self) -> &RX_LPI_USEC_CNTR

0x7f4 - Rx LPI microsecond counter register

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pub fn rx_lpi_tran_cntr(&self) -> &RX_LPI_TRAN_CNTR

0x7f8 - Rx LPI transition counter register

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pub fn macl3l4c0r(&self) -> &MACL3L4C0R

0x900 - L3 and L4 control 0 register

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pub fn macl4a0r(&self) -> &MACL4A0R

0x904 - Layer4 Address filter 0 register

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pub fn macl3a00r(&self) -> &MACL3A00R

0x910 - Layer3 Address 0 filter 0 register

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pub fn macl3a10r(&self) -> &MACL3A10R

0x914 - Layer3 Address 1 filter 0 register

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pub fn macl3a20r(&self) -> &MACL3A20R

0x918 - Layer3 Address 2 filter 0 register

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pub fn macl3a30r(&self) -> &MACL3A30R

0x91c - Layer3 Address 3 filter 0 register

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pub fn macl3l4c1r(&self) -> &MACL3L4C1R

0x930 - L3 and L4 control 1 register

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pub fn macl4a1r(&self) -> &MACL4A1R

0x934 - Layer 4 address filter 1 register

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pub fn macl3a01r(&self) -> &MACL3A01R

0x940 - Layer3 address 0 filter 1 Register

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pub fn macl3a11r(&self) -> &MACL3A11R

0x944 - Layer3 address 1 filter 1 register

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pub fn macl3a21r(&self) -> &MACL3A21R

0x948 - Layer3 address 2 filter 1 Register

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pub fn macl3a31r(&self) -> &MACL3A31R

0x94c - Layer3 address 3 filter 1 register

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pub fn mactscr(&self) -> &MACTSCR

0xb00 - Timestamp control Register

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pub fn macssir(&self) -> &MACSSIR

0xb04 - Subsecond increment register

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pub fn macstsr(&self) -> &MACSTSR

0xb08 - System time seconds register

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pub fn macstnr(&self) -> &MACSTNR

0xb0c - System time nanoseconds register

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pub fn macstsur(&self) -> &MACSTSUR

0xb10 - System time seconds update register

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pub fn macstnur(&self) -> &MACSTNUR

0xb14 - System time nanoseconds update register

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pub fn mactsar(&self) -> &MACTSAR

0xb18 - Timestamp addend register

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pub fn mactssr(&self) -> &MACTSSR

0xb20 - Timestamp status register

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pub fn mactxtssnr(&self) -> &MACTXTSSNR

0xb30 - Tx timestamp status nanoseconds register

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pub fn mactxtsssr(&self) -> &MACTXTSSSR

0xb34 - Tx timestamp status seconds register

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pub fn macacr(&self) -> &MACACR

0xb40 - Auxiliary control register

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pub fn macatsnr(&self) -> &MACATSNR

0xb48 - Auxiliary timestamp nanoseconds register

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pub fn macatssr(&self) -> &MACATSSR

0xb4c - Auxiliary timestamp seconds register

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pub fn mactsiacr(&self) -> &MACTSIACR

0xb50 - Timestamp Ingress asymmetric correction register

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pub fn mactseacr(&self) -> &MACTSEACR

0xb54 - Timestamp Egress asymmetric correction register

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pub fn mactsicnr(&self) -> &MACTSICNR

0xb58 - Timestamp Ingress correction nanosecond register

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pub fn mactsecnr(&self) -> &MACTSECNR

0xb5c - Timestamp Egress correction nanosecond register

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pub fn macppscr_alternate(&self) -> &MACPPSCR_ALTERNATE

0xb70 - PPS control register

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pub fn macppscr(&self) -> &MACPPSCR

0xb70 - PPS control register

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pub fn macppsttsr(&self) -> &MACPPSTTSR

0xb80 - PPS target time seconds register

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pub fn macppsttnr(&self) -> &MACPPSTTNR

0xb84 - PPS target time nanoseconds register

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pub fn macppsir(&self) -> &MACPPSIR

0xb88 - PPS interval register

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pub fn macppswr(&self) -> &MACPPSWR

0xb8c - PPS width register

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pub fn macpocr(&self) -> &MACPOCR

0xbc0 - PTP Offload control register

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pub fn macspi0r(&self) -> &MACSPI0R

0xbc4 - PTP Source Port Identity 0 Register

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pub fn macspi1r(&self) -> &MACSPI1R

0xbc8 - PTP Source port identity 1 register

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pub fn macspi2r(&self) -> &MACSPI2R

0xbcc - PTP Source port identity 2 register

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pub fn maclmir(&self) -> &MACLMIR

0xbd0 - Log message interval register

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pub fn mtlomr(&self) -> &MTLOMR

0xc00 - Operating mode Register

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pub fn mtlisr(&self) -> &MTLISR

0xc20 - Interrupt status Register

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pub fn mtltxqomr(&self) -> &MTLTXQOMR

0xd00 - Tx queue operating mode Register

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pub fn mtltxqur(&self) -> &MTLTXQUR

0xd04 - Tx queue underflow register

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pub fn mtltxqdr(&self) -> &MTLTXQDR

0xd08 - Tx queue debug register

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pub fn mtlqicsr(&self) -> &MTLQICSR

0xd2c - Queue interrupt control status Register

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pub fn mtlrxqomr(&self) -> &MTLRXQOMR

0xd30 - Rx queue operating mode register

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pub fn mtlrxqmpocr(&self) -> &MTLRXQMPOCR

0xd34 - Rx queue missed packet and overflow counter register

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pub fn mtlrxqdr(&self) -> &MTLRXQDR

0xd38 - Rx queue debug register

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pub fn dmamr(&self) -> &DMAMR

0x1000 - DMA mode register

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pub fn dmasbmr(&self) -> &DMASBMR

0x1004 - System bus mode register

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pub fn dmaisr(&self) -> &DMAISR

0x1008 - Interrupt status register

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pub fn dmadsr(&self) -> &DMADSR

0x100c - Debug status register

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pub fn dmaccr(&self) -> &DMACCR

0x1100 - Channel control register

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pub fn dmactxcr(&self) -> &DMACTXCR

0x1104 - Channel transmit control register

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pub fn dmacrxcr(&self) -> &DMACRXCR

0x1108 - Channel receive control register

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pub fn dmactxdlar(&self) -> &DMACTXDLAR

0x1114 - Channel Tx descriptor list address register

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pub fn dmacrxdlar(&self) -> &DMACRXDLAR

0x111c - Channel Rx descriptor list address register

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pub fn dmactxdtpr(&self) -> &DMACTXDTPR

0x1120 - Channel Tx descriptor tail pointer register

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pub fn dmacrxdtpr(&self) -> &DMACRXDTPR

0x1128 - Channel Rx descriptor tail pointer register

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pub fn dmactxrlr(&self) -> &DMACTXRLR

0x112c - Channel Tx descriptor ring length register

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pub fn dmacrxrlr(&self) -> &DMACRXRLR

0x1130 - Channel Rx descriptor ring length register

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pub fn dmacier(&self) -> &DMACIER

0x1134 - Channel interrupt enable register

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pub fn dmacrxiwtr(&self) -> &DMACRXIWTR

0x1138 - Channel Rx interrupt watchdog timer register

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pub fn dmaccatxdr(&self) -> &DMACCATXDR

0x1144 - Channel current application transmit descriptor register

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pub fn dmaccarxdr(&self) -> &DMACCARXDR

0x114c - Channel current application receive descriptor register

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pub fn dmaccatxbr(&self) -> &DMACCATXBR

0x1154 - Channel current application transmit buffer register

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pub fn dmaccarxbr(&self) -> &DMACCARXBR

0x115c - Channel current application receive buffer register

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pub fn dmacsr(&self) -> &DMACSR

0x1160 - Channel status register

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pub fn dmacmfcr(&self) -> &DMACMFCR

0x116c - Channel missed frame count register

Trait Implementations§

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impl Debug for SEC_ETH

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Deref for SEC_ETH

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type Target = RegisterBlock

The resulting type after dereferencing.
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fn deref(&self) -> &Self::Target

Dereferences the value.
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impl Send for SEC_ETH

Auto Trait Implementations§

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where T: 'static + ?Sized,

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Gets the TypeId of self. Read more
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where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

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impl<P, T> Receiver for P
where P: Deref<Target = T> + ?Sized, T: ?Sized,

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type Target = T

🔬This is a nightly-only experimental API. (arbitrary_self_types)
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where U: Into<T>,

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type Error = Infallible

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Performs the conversion.
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where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.