1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
#[doc = "Register `CCR5` reader"]
pub struct R(crate::R<CCR5_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCR5_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCR5_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCR5` writer"]
pub struct W(crate::W<CCR5_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCR5_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCR5_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - channel enable"]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `EN` writer - channel enable"]
pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR5_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - TCIE"]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - TCIE"]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR5_SPEC, bool, O>;
#[doc = "Field `HTIE` reader - HTIE"]
pub type HTIE_R = crate::BitReader<bool>;
#[doc = "Field `HTIE` writer - HTIE"]
pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR5_SPEC, bool, O>;
#[doc = "Field `TEIE` reader - TEIE"]
pub type TEIE_R = crate::BitReader<bool>;
#[doc = "Field `TEIE` writer - TEIE"]
pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR5_SPEC, bool, O>;
#[doc = "Field `DIR` reader - DIR"]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - DIR"]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR5_SPEC, bool, O>;
#[doc = "Field `CIRC` reader - CIRC"]
pub type CIRC_R = crate::BitReader<bool>;
#[doc = "Field `CIRC` writer - CIRC"]
pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR5_SPEC, bool, O>;
#[doc = "Field `PINC` reader - PINC"]
pub type PINC_R = crate::BitReader<bool>;
#[doc = "Field `PINC` writer - PINC"]
pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR5_SPEC, bool, O>;
#[doc = "Field `MINC` reader - MINC"]
pub type MINC_R = crate::BitReader<bool>;
#[doc = "Field `MINC` writer - MINC"]
pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR5_SPEC, bool, O>;
#[doc = "Field `PSIZE` reader - PSIZE"]
pub type PSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSIZE` writer - PSIZE"]
pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR5_SPEC, u8, u8, 2, O>;
#[doc = "Field `MSIZE` reader - MSIZE"]
pub type MSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MSIZE` writer - MSIZE"]
pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR5_SPEC, u8, u8, 2, O>;
#[doc = "Field `PL` reader - PL"]
pub type PL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PL` writer - PL"]
pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR5_SPEC, u8, u8, 2, O>;
#[doc = "Field `MEM2MEM` reader - MEM2MEM"]
pub type MEM2MEM_R = crate::BitReader<bool>;
#[doc = "Field `MEM2MEM` writer - MEM2MEM"]
pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR5_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - channel enable"]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - TCIE"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - HTIE"]
#[inline(always)]
pub fn htie(&self) -> HTIE_R {
HTIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - TEIE"]
#[inline(always)]
pub fn teie(&self) -> TEIE_R {
TEIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - DIR"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - CIRC"]
#[inline(always)]
pub fn circ(&self) -> CIRC_R {
CIRC_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - PINC"]
#[inline(always)]
pub fn pinc(&self) -> PINC_R {
PINC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - MINC"]
#[inline(always)]
pub fn minc(&self) -> MINC_R {
MINC_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - PSIZE"]
#[inline(always)]
pub fn psize(&self) -> PSIZE_R {
PSIZE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - MSIZE"]
#[inline(always)]
pub fn msize(&self) -> MSIZE_R {
MSIZE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - PL"]
#[inline(always)]
pub fn pl(&self) -> PL_R {
PL_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - MEM2MEM"]
#[inline(always)]
pub fn mem2mem(&self) -> MEM2MEM_R {
MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - channel enable"]
#[inline(always)]
pub fn en(&mut self) -> EN_W<0> {
EN_W::new(self)
}
#[doc = "Bit 1 - TCIE"]
#[inline(always)]
pub fn tcie(&mut self) -> TCIE_W<1> {
TCIE_W::new(self)
}
#[doc = "Bit 2 - HTIE"]
#[inline(always)]
pub fn htie(&mut self) -> HTIE_W<2> {
HTIE_W::new(self)
}
#[doc = "Bit 3 - TEIE"]
#[inline(always)]
pub fn teie(&mut self) -> TEIE_W<3> {
TEIE_W::new(self)
}
#[doc = "Bit 4 - DIR"]
#[inline(always)]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bit 5 - CIRC"]
#[inline(always)]
pub fn circ(&mut self) -> CIRC_W<5> {
CIRC_W::new(self)
}
#[doc = "Bit 6 - PINC"]
#[inline(always)]
pub fn pinc(&mut self) -> PINC_W<6> {
PINC_W::new(self)
}
#[doc = "Bit 7 - MINC"]
#[inline(always)]
pub fn minc(&mut self) -> MINC_W<7> {
MINC_W::new(self)
}
#[doc = "Bits 8:9 - PSIZE"]
#[inline(always)]
pub fn psize(&mut self) -> PSIZE_W<8> {
PSIZE_W::new(self)
}
#[doc = "Bits 10:11 - MSIZE"]
#[inline(always)]
pub fn msize(&mut self) -> MSIZE_W<10> {
MSIZE_W::new(self)
}
#[doc = "Bits 12:13 - PL"]
#[inline(always)]
pub fn pl(&mut self) -> PL_W<12> {
PL_W::new(self)
}
#[doc = "Bit 14 - MEM2MEM"]
#[inline(always)]
pub fn mem2mem(&mut self) -> MEM2MEM_W<14> {
MEM2MEM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA channel 4 configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr5](index.html) module"]
pub struct CCR5_SPEC;
impl crate::RegisterSpec for CCR5_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccr5::R](R) reader structure"]
impl crate::Readable for CCR5_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccr5::W](W) writer structure"]
impl crate::Writable for CCR5_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CCR5 to value 0"]
impl crate::Resettable for CCR5_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}
