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#[doc = "Reader of register CCIPR"] pub type R = crate::R<u32, super::CCIPR>; #[doc = "Writer for register CCIPR"] pub type W = crate::W<u32, super::CCIPR>; #[doc = "Register CCIPR `reset()`'s with value 0"] impl crate::ResetValue for super::CCIPR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `ADC345SEL`"] pub type ADC345SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `ADC345SEL`"] pub struct ADC345SEL_W<'a> { w: &'a mut W, } impl<'a> ADC345SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30); self.w } } #[doc = "Reader of field `ADC12SEL`"] pub type ADC12SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `ADC12SEL`"] pub struct ADC12SEL_W<'a> { w: &'a mut W, } impl<'a> ADC12SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28); self.w } } #[doc = "Reader of field `CLK48SEL`"] pub type CLK48SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `CLK48SEL`"] pub struct CLK48SEL_W<'a> { w: &'a mut W, } impl<'a> CLK48SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26); self.w } } #[doc = "Reader of field `FDCANSEL`"] pub type FDCANSEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `FDCANSEL`"] pub struct FDCANSEL_W<'a> { w: &'a mut W, } impl<'a> FDCANSEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24); self.w } } #[doc = "Reader of field `I2S23SEL`"] pub type I2S23SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `I2S23SEL`"] pub struct I2S23SEL_W<'a> { w: &'a mut W, } impl<'a> I2S23SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22); self.w } } #[doc = "Reader of field `SAI1SEL`"] pub type SAI1SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `SAI1SEL`"] pub struct SAI1SEL_W<'a> { w: &'a mut W, } impl<'a> SAI1SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20); self.w } } #[doc = "Reader of field `LPTIM1SEL`"] pub type LPTIM1SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `LPTIM1SEL`"] pub struct LPTIM1SEL_W<'a> { w: &'a mut W, } impl<'a> LPTIM1SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18); self.w } } #[doc = "Reader of field `I2C3SEL`"] pub type I2C3SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `I2C3SEL`"] pub struct I2C3SEL_W<'a> { w: &'a mut W, } impl<'a> I2C3SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16); self.w } } #[doc = "Reader of field `I2C2SEL`"] pub type I2C2SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `I2C2SEL`"] pub struct I2C2SEL_W<'a> { w: &'a mut W, } impl<'a> I2C2SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14); self.w } } #[doc = "Reader of field `I2C1SEL`"] pub type I2C1SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `I2C1SEL`"] pub struct I2C1SEL_W<'a> { w: &'a mut W, } impl<'a> I2C1SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12); self.w } } #[doc = "Reader of field `LPUART1SEL`"] pub type LPUART1SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `LPUART1SEL`"] pub struct LPUART1SEL_W<'a> { w: &'a mut W, } impl<'a> LPUART1SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10); self.w } } #[doc = "Reader of field `UART5SEL`"] pub type UART5SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `UART5SEL`"] pub struct UART5SEL_W<'a> { w: &'a mut W, } impl<'a> UART5SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); self.w } } #[doc = "Reader of field `UART4SEL`"] pub type UART4SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `UART4SEL`"] pub struct UART4SEL_W<'a> { w: &'a mut W, } impl<'a> UART4SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6); self.w } } #[doc = "Reader of field `USART3SEL`"] pub type USART3SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `USART3SEL`"] pub struct USART3SEL_W<'a> { w: &'a mut W, } impl<'a> USART3SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4); self.w } } #[doc = "Reader of field `USART2SEL`"] pub type USART2SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `USART2SEL`"] pub struct USART2SEL_W<'a> { w: &'a mut W, } impl<'a> USART2SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2); self.w } } #[doc = "Reader of field `USART1SEL`"] pub type USART1SEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `USART1SEL`"] pub struct USART1SEL_W<'a> { w: &'a mut W, } impl<'a> USART1SEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); self.w } } impl R { #[doc = "Bits 30:31 - ADC3/4/5 clock source selection"] #[inline(always)] pub fn adc345sel(&self) -> ADC345SEL_R { ADC345SEL_R::new(((self.bits >> 30) & 0x03) as u8) } #[doc = "Bits 28:29 - ADCs clock source selection"] #[inline(always)] pub fn adc12sel(&self) -> ADC12SEL_R { ADC12SEL_R::new(((self.bits >> 28) & 0x03) as u8) } #[doc = "Bits 26:27 - 48 MHz clock source selection"] #[inline(always)] pub fn clk48sel(&self) -> CLK48SEL_R { CLK48SEL_R::new(((self.bits >> 26) & 0x03) as u8) } #[doc = "Bits 24:25 - SAI2 clock source selection"] #[inline(always)] pub fn fdcansel(&self) -> FDCANSEL_R { FDCANSEL_R::new(((self.bits >> 24) & 0x03) as u8) } #[doc = "Bits 22:23 - SAI1 clock source selection"] #[inline(always)] pub fn i2s23sel(&self) -> I2S23SEL_R { I2S23SEL_R::new(((self.bits >> 22) & 0x03) as u8) } #[doc = "Bits 20:21 - Low power timer 2 clock source selection"] #[inline(always)] pub fn sai1sel(&self) -> SAI1SEL_R { SAI1SEL_R::new(((self.bits >> 20) & 0x03) as u8) } #[doc = "Bits 18:19 - Low power timer 1 clock source selection"] #[inline(always)] pub fn lptim1sel(&self) -> LPTIM1SEL_R { LPTIM1SEL_R::new(((self.bits >> 18) & 0x03) as u8) } #[doc = "Bits 16:17 - I2C3 clock source selection"] #[inline(always)] pub fn i2c3sel(&self) -> I2C3SEL_R { I2C3SEL_R::new(((self.bits >> 16) & 0x03) as u8) } #[doc = "Bits 14:15 - I2C2 clock source selection"] #[inline(always)] pub fn i2c2sel(&self) -> I2C2SEL_R { I2C2SEL_R::new(((self.bits >> 14) & 0x03) as u8) } #[doc = "Bits 12:13 - I2C1 clock source selection"] #[inline(always)] pub fn i2c1sel(&self) -> I2C1SEL_R { I2C1SEL_R::new(((self.bits >> 12) & 0x03) as u8) } #[doc = "Bits 10:11 - LPUART1 clock source selection"] #[inline(always)] pub fn lpuart1sel(&self) -> LPUART1SEL_R { LPUART1SEL_R::new(((self.bits >> 10) & 0x03) as u8) } #[doc = "Bits 8:9 - UART5 clock source selection"] #[inline(always)] pub fn uart5sel(&self) -> UART5SEL_R { UART5SEL_R::new(((self.bits >> 8) & 0x03) as u8) } #[doc = "Bits 6:7 - UART4 clock source selection"] #[inline(always)] pub fn uart4sel(&self) -> UART4SEL_R { UART4SEL_R::new(((self.bits >> 6) & 0x03) as u8) } #[doc = "Bits 4:5 - USART3 clock source selection"] #[inline(always)] pub fn usart3sel(&self) -> USART3SEL_R { USART3SEL_R::new(((self.bits >> 4) & 0x03) as u8) } #[doc = "Bits 2:3 - USART2 clock source selection"] #[inline(always)] pub fn usart2sel(&self) -> USART2SEL_R { USART2SEL_R::new(((self.bits >> 2) & 0x03) as u8) } #[doc = "Bits 0:1 - USART1 clock source selection"] #[inline(always)] pub fn usart1sel(&self) -> USART1SEL_R { USART1SEL_R::new((self.bits & 0x03) as u8) } } impl W { #[doc = "Bits 30:31 - ADC3/4/5 clock source selection"] #[inline(always)] pub fn adc345sel(&mut self) -> ADC345SEL_W { ADC345SEL_W { w: self } } #[doc = "Bits 28:29 - ADCs clock source selection"] #[inline(always)] pub fn adc12sel(&mut self) -> ADC12SEL_W { ADC12SEL_W { w: self } } #[doc = "Bits 26:27 - 48 MHz clock source selection"] #[inline(always)] pub fn clk48sel(&mut self) -> CLK48SEL_W { CLK48SEL_W { w: self } } #[doc = "Bits 24:25 - SAI2 clock source selection"] #[inline(always)] pub fn fdcansel(&mut self) -> FDCANSEL_W { FDCANSEL_W { w: self } } #[doc = "Bits 22:23 - SAI1 clock source selection"] #[inline(always)] pub fn i2s23sel(&mut self) -> I2S23SEL_W { I2S23SEL_W { w: self } } #[doc = "Bits 20:21 - Low power timer 2 clock source selection"] #[inline(always)] pub fn sai1sel(&mut self) -> SAI1SEL_W { SAI1SEL_W { w: self } } #[doc = "Bits 18:19 - Low power timer 1 clock source selection"] #[inline(always)] pub fn lptim1sel(&mut self) -> LPTIM1SEL_W { LPTIM1SEL_W { w: self } } #[doc = "Bits 16:17 - I2C3 clock source selection"] #[inline(always)] pub fn i2c3sel(&mut self) -> I2C3SEL_W { I2C3SEL_W { w: self } } #[doc = "Bits 14:15 - I2C2 clock source selection"] #[inline(always)] pub fn i2c2sel(&mut self) -> I2C2SEL_W { I2C2SEL_W { w: self } } #[doc = "Bits 12:13 - I2C1 clock source selection"] #[inline(always)] pub fn i2c1sel(&mut self) -> I2C1SEL_W { I2C1SEL_W { w: self } } #[doc = "Bits 10:11 - LPUART1 clock source selection"] #[inline(always)] pub fn lpuart1sel(&mut self) -> LPUART1SEL_W { LPUART1SEL_W { w: self } } #[doc = "Bits 8:9 - UART5 clock source selection"] #[inline(always)] pub fn uart5sel(&mut self) -> UART5SEL_W { UART5SEL_W { w: self } } #[doc = "Bits 6:7 - UART4 clock source selection"] #[inline(always)] pub fn uart4sel(&mut self) -> UART4SEL_W { UART4SEL_W { w: self } } #[doc = "Bits 4:5 - USART3 clock source selection"] #[inline(always)] pub fn usart3sel(&mut self) -> USART3SEL_W { USART3SEL_W { w: self } } #[doc = "Bits 2:3 - USART2 clock source selection"] #[inline(always)] pub fn usart2sel(&mut self) -> USART2SEL_W { USART2SEL_W { w: self } } #[doc = "Bits 0:1 - USART1 clock source selection"] #[inline(always)] pub fn usart1sel(&mut self) -> USART1SEL_W { USART1SEL_W { w: self } } }