Expand description
DAC status register
Structs
Type Definitions
Field BWST1 reader - DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).
Field BWST2 reader - DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). Note: This bit is available only on dual-channel DACs. Refer to implementation.
Field CAL_FLAG1 reader - DAC channel1 calibration offset status This bit is set and cleared by hardware
Field CAL_FLAG2 reader - DAC channel2 calibration offset status This bit is set and cleared by hardware Note: This bit is available only on dual-channel DACs. Refer to implementation.
Field DMAUDR1 reader - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
Field DMAUDR1 writer - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
Field DMAUDR2 reader - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). Note: This bit is available only on dual-channel DACs. Refer to implementation.
Field DMAUDR2 writer - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). Note: This bit is available only on dual-channel DACs. Refer to implementation.