Expand description
ADC Analog Watchdog 3 Configuration register
Re-exports
pub use AWD3CH0_A as AWD3CH1_A;pub use AWD3CH0_A as AWD3CH2_A;pub use AWD3CH0_A as AWD3CH3_A;pub use AWD3CH0_A as AWD3CH4_A;pub use AWD3CH0_A as AWD3CH5_A;pub use AWD3CH0_A as AWD3CH6_A;pub use AWD3CH0_A as AWD3CH7_A;pub use AWD3CH0_A as AWD3CH8_A;pub use AWD3CH0_A as AWD3CH9_A;pub use AWD3CH0_A as AWD3CH10_A;pub use AWD3CH0_A as AWD3CH11_A;pub use AWD3CH0_A as AWD3CH12_A;pub use AWD3CH0_A as AWD3CH13_A;pub use AWD3CH0_A as AWD3CH14_A;pub use AWD3CH0_A as AWD3CH15_A;pub use AWD3CH0_A as AWD3CH16_A;pub use AWD3CH0_A as AWD3CH17_A;pub use AWD3CH0_A as AWD3CH18_A;pub use AWD3CH0_R as AWD3CH1_R;pub use AWD3CH0_R as AWD3CH2_R;pub use AWD3CH0_R as AWD3CH3_R;pub use AWD3CH0_R as AWD3CH4_R;pub use AWD3CH0_R as AWD3CH5_R;pub use AWD3CH0_R as AWD3CH6_R;pub use AWD3CH0_R as AWD3CH7_R;pub use AWD3CH0_R as AWD3CH8_R;pub use AWD3CH0_R as AWD3CH9_R;pub use AWD3CH0_R as AWD3CH10_R;pub use AWD3CH0_R as AWD3CH11_R;pub use AWD3CH0_R as AWD3CH12_R;pub use AWD3CH0_R as AWD3CH13_R;pub use AWD3CH0_R as AWD3CH14_R;pub use AWD3CH0_R as AWD3CH15_R;pub use AWD3CH0_R as AWD3CH16_R;pub use AWD3CH0_R as AWD3CH17_R;pub use AWD3CH0_R as AWD3CH18_R;pub use AWD3CH0_W as AWD3CH1_W;pub use AWD3CH0_W as AWD3CH2_W;pub use AWD3CH0_W as AWD3CH3_W;pub use AWD3CH0_W as AWD3CH4_W;pub use AWD3CH0_W as AWD3CH5_W;pub use AWD3CH0_W as AWD3CH6_W;pub use AWD3CH0_W as AWD3CH7_W;pub use AWD3CH0_W as AWD3CH8_W;pub use AWD3CH0_W as AWD3CH9_W;pub use AWD3CH0_W as AWD3CH10_W;pub use AWD3CH0_W as AWD3CH11_W;pub use AWD3CH0_W as AWD3CH12_W;pub use AWD3CH0_W as AWD3CH13_W;pub use AWD3CH0_W as AWD3CH14_W;pub use AWD3CH0_W as AWD3CH15_W;pub use AWD3CH0_W as AWD3CH16_W;pub use AWD3CH0_W as AWD3CH17_W;pub use AWD3CH0_W as AWD3CH18_W;Structs
ADC Analog Watchdog 3 Configuration register
Register AWD3CR reader
Register AWD3CR writer
Enums
Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
Type Definitions
Field AWD3CH0 reader - Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0]
for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
Field AWD3CH0 writer - Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0]
for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).