Expand description
Guard time and prescaler register
Structs
Type Definitions
Field GT reader - Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
Field GT writer - Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
Field PSC reader - Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0]
= IrDA Normal and Low-Power baud rate PSC[7:0]
is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0]
is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: … 0010Â 0000: Divides the source clock by 32 (IrDA mode) … 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5]
must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to ’0â when the Smartcard and IrDA modes are not supported. Refer to .
Field PSC writer - Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0]
= IrDA Normal and Low-Power baud rate PSC[7:0]
is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0]
is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: … 0010Â 0000: Divides the source clock by 32 (IrDA mode) … 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5]
must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to ’0â when the Smartcard and IrDA modes are not supported. Refer to .