stm32g0/stm32g0c1/
ucpd1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cfgr1: CFGR1,
6    cfgr2: CFGR2,
7    cfgr3: CFGR3,
8    cr: CR,
9    imr: IMR,
10    sr: SR,
11    icr: ICR,
12    tx_ordsetr: TX_ORDSETR,
13    tx_payszr: TX_PAYSZR,
14    txdr: TXDR,
15    rx_ordsetr: RX_ORDSETR,
16    rx_payszr: RX_PAYSZR,
17    rxdr: RXDR,
18    rx_ordextr1: RX_ORDEXTR1,
19    rx_ordextr2: RX_ORDEXTR2,
20}
21impl RegisterBlock {
22    ///0x00 - UCPD configuration register 1
23    #[inline(always)]
24    pub const fn cfgr1(&self) -> &CFGR1 {
25        &self.cfgr1
26    }
27    ///0x04 - UCPD configuration register 2
28    #[inline(always)]
29    pub const fn cfgr2(&self) -> &CFGR2 {
30        &self.cfgr2
31    }
32    ///0x08 - UCPD configuration register 3
33    #[inline(always)]
34    pub const fn cfgr3(&self) -> &CFGR3 {
35        &self.cfgr3
36    }
37    ///0x0c - UCPD control register
38    #[inline(always)]
39    pub const fn cr(&self) -> &CR {
40        &self.cr
41    }
42    ///0x10 - UCPD interrupt mask register
43    #[inline(always)]
44    pub const fn imr(&self) -> &IMR {
45        &self.imr
46    }
47    ///0x14 - UCPD status register
48    #[inline(always)]
49    pub const fn sr(&self) -> &SR {
50        &self.sr
51    }
52    ///0x18 - UCPD interrupt clear register
53    #[inline(always)]
54    pub const fn icr(&self) -> &ICR {
55        &self.icr
56    }
57    ///0x1c - UCPD Tx ordered set type register
58    #[inline(always)]
59    pub const fn tx_ordsetr(&self) -> &TX_ORDSETR {
60        &self.tx_ordsetr
61    }
62    ///0x20 - UCPD Tx payload size register
63    #[inline(always)]
64    pub const fn tx_payszr(&self) -> &TX_PAYSZR {
65        &self.tx_payszr
66    }
67    ///0x24 - UCPD Tx data register
68    #[inline(always)]
69    pub const fn txdr(&self) -> &TXDR {
70        &self.txdr
71    }
72    ///0x28 - UCPD Rx ordered set register
73    #[inline(always)]
74    pub const fn rx_ordsetr(&self) -> &RX_ORDSETR {
75        &self.rx_ordsetr
76    }
77    ///0x2c - UCPD Rx payload size register
78    #[inline(always)]
79    pub const fn rx_payszr(&self) -> &RX_PAYSZR {
80        &self.rx_payszr
81    }
82    ///0x30 - UCPD receive data register
83    #[inline(always)]
84    pub const fn rxdr(&self) -> &RXDR {
85        &self.rxdr
86    }
87    ///0x34 - UCPD Rx ordered set extension register 1
88    #[inline(always)]
89    pub const fn rx_ordextr1(&self) -> &RX_ORDEXTR1 {
90        &self.rx_ordextr1
91    }
92    ///0x38 - UCPD Rx ordered set extension register 2
93    #[inline(always)]
94    pub const fn rx_ordextr2(&self) -> &RX_ORDEXTR2 {
95        &self.rx_ordextr2
96    }
97}
98/**CFGR1 (rw) register accessor: UCPD configuration register 1
99
100You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
101
102See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:CFGR1)
103
104For information about available fields see [`mod@cfgr1`] module*/
105pub type CFGR1 = crate::Reg<cfgr1::CFGR1rs>;
106///UCPD configuration register 1
107pub mod cfgr1;
108/**CFGR2 (rw) register accessor: UCPD configuration register 2
109
110You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
111
112See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:CFGR2)
113
114For information about available fields see [`mod@cfgr2`] module*/
115pub type CFGR2 = crate::Reg<cfgr2::CFGR2rs>;
116///UCPD configuration register 2
117pub mod cfgr2;
118/**CFGR3 (rw) register accessor: UCPD configuration register 3
119
120You can [`read`](crate::Reg::read) this register and get [`cfgr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
121
122See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:CFGR3)
123
124For information about available fields see [`mod@cfgr3`] module*/
125pub type CFGR3 = crate::Reg<cfgr3::CFGR3rs>;
126///UCPD configuration register 3
127pub mod cfgr3;
128/**CR (rw) register accessor: UCPD control register
129
130You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
131
132See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:CR)
133
134For information about available fields see [`mod@cr`] module*/
135pub type CR = crate::Reg<cr::CRrs>;
136///UCPD control register
137pub mod cr;
138/**IMR (rw) register accessor: UCPD interrupt mask register
139
140You can [`read`](crate::Reg::read) this register and get [`imr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
141
142See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:IMR)
143
144For information about available fields see [`mod@imr`] module*/
145pub type IMR = crate::Reg<imr::IMRrs>;
146///UCPD interrupt mask register
147pub mod imr;
148/**SR (r) register accessor: UCPD status register
149
150You can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
151
152See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:SR)
153
154For information about available fields see [`mod@sr`] module*/
155pub type SR = crate::Reg<sr::SRrs>;
156///UCPD status register
157pub mod sr;
158/**ICR (w) register accessor: UCPD interrupt clear register
159
160You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:ICR)
163
164For information about available fields see [`mod@icr`] module*/
165pub type ICR = crate::Reg<icr::ICRrs>;
166///UCPD interrupt clear register
167pub mod icr;
168/**TX_ORDSETR (rw) register accessor: UCPD Tx ordered set type register
169
170You can [`read`](crate::Reg::read) this register and get [`tx_ordsetr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_ordsetr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
171
172See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:TX_ORDSETR)
173
174For information about available fields see [`mod@tx_ordsetr`] module*/
175pub type TX_ORDSETR = crate::Reg<tx_ordsetr::TX_ORDSETRrs>;
176///UCPD Tx ordered set type register
177pub mod tx_ordsetr;
178/**TX_PAYSZR (rw) register accessor: UCPD Tx payload size register
179
180You can [`read`](crate::Reg::read) this register and get [`tx_payszr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_payszr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
181
182See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:TX_PAYSZR)
183
184For information about available fields see [`mod@tx_payszr`] module*/
185pub type TX_PAYSZR = crate::Reg<tx_payszr::TX_PAYSZRrs>;
186///UCPD Tx payload size register
187pub mod tx_payszr;
188/**TXDR (rw) register accessor: UCPD Tx data register
189
190You can [`read`](crate::Reg::read) this register and get [`txdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
191
192See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:TXDR)
193
194For information about available fields see [`mod@txdr`] module*/
195pub type TXDR = crate::Reg<txdr::TXDRrs>;
196///UCPD Tx data register
197pub mod txdr;
198/**RX_ORDSETR (r) register accessor: UCPD Rx ordered set register
199
200You can [`read`](crate::Reg::read) this register and get [`rx_ordsetr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
201
202See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:RX_ORDSETR)
203
204For information about available fields see [`mod@rx_ordsetr`] module*/
205pub type RX_ORDSETR = crate::Reg<rx_ordsetr::RX_ORDSETRrs>;
206///UCPD Rx ordered set register
207pub mod rx_ordsetr;
208/**RX_PAYSZR (r) register accessor: UCPD Rx payload size register
209
210You can [`read`](crate::Reg::read) this register and get [`rx_payszr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
211
212See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:RX_PAYSZR)
213
214For information about available fields see [`mod@rx_payszr`] module*/
215pub type RX_PAYSZR = crate::Reg<rx_payszr::RX_PAYSZRrs>;
216///UCPD Rx payload size register
217pub mod rx_payszr;
218/**RXDR (r) register accessor: UCPD receive data register
219
220You can [`read`](crate::Reg::read) this register and get [`rxdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
221
222See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:RXDR)
223
224For information about available fields see [`mod@rxdr`] module*/
225pub type RXDR = crate::Reg<rxdr::RXDRrs>;
226///UCPD receive data register
227pub mod rxdr;
228/**RX_ORDEXTR1 (rw) register accessor: UCPD Rx ordered set extension register 1
229
230You can [`read`](crate::Reg::read) this register and get [`rx_ordextr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_ordextr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
231
232See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:RX_ORDEXTR1)
233
234For information about available fields see [`mod@rx_ordextr1`] module*/
235pub type RX_ORDEXTR1 = crate::Reg<rx_ordextr1::RX_ORDEXTR1rs>;
236///UCPD Rx ordered set extension register 1
237pub mod rx_ordextr1;
238/**RX_ORDEXTR2 (rw) register accessor: UCPD Rx ordered set extension register 2
239
240You can [`read`](crate::Reg::read) this register and get [`rx_ordextr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_ordextr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
241
242See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#UCPD1:RX_ORDEXTR2)
243
244For information about available fields see [`mod@rx_ordextr2`] module*/
245pub type RX_ORDEXTR2 = crate::Reg<rx_ordextr2::RX_ORDEXTR2rs>;
246///UCPD Rx ordered set extension register 2
247pub mod rx_ordextr2;
stm32g0/stm32g0c1/ucpd1.rs

stm32g0/stm32g0c1/
ucpd1.rs
