stm32g0/stm32g0c1/
fdcan1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    crel: CREL,
6    endn: ENDN,
7    _reserved2: [u8; 0x04],
8    dbtp: DBTP,
9    test: TEST,
10    rwd: RWD,
11    cccr: CCCR,
12    nbtp: NBTP,
13    tscc: TSCC,
14    tscv: TSCV,
15    tocc: TOCC,
16    tocv: TOCV,
17    _reserved11: [u8; 0x10],
18    ecr: ECR,
19    psr: PSR,
20    tdcr: TDCR,
21    _reserved14: [u8; 0x04],
22    ir: IR,
23    ie: IE,
24    ils: ILS,
25    ile: ILE,
26    _reserved18: [u8; 0x20],
27    rxgfc: RXGFC,
28    xidam: XIDAM,
29    hpms: HPMS,
30    _reserved21: [u8; 0x04],
31    rxf0s: RXF0S,
32    rxf0a: RXF0A,
33    rxf1s: RXF1S,
34    rxf1a: RXF1A,
35    _reserved25: [u8; 0x20],
36    txbc: TXBC,
37    txfqs: TXFQS,
38    txbrp: TXBRP,
39    txbar: TXBAR,
40    txbcr: TXBCR,
41    txbto: TXBTO,
42    txbcf: TXBCF,
43    txbtie: TXBTIE,
44    txbcie: TXBCIE,
45    txefs: TXEFS,
46    txefa: TXEFA,
47    _reserved36: [u8; 0x14],
48    ckdiv: CKDIV,
49}
50impl RegisterBlock {
51    ///0x00 - FDCAN core release register
52    #[inline(always)]
53    pub const fn crel(&self) -> &CREL {
54        &self.crel
55    }
56    ///0x04 - FDCAN endian register
57    #[inline(always)]
58    pub const fn endn(&self) -> &ENDN {
59        &self.endn
60    }
61    ///0x0c - FDCAN data bit timing and prescaler register
62    #[inline(always)]
63    pub const fn dbtp(&self) -> &DBTP {
64        &self.dbtp
65    }
66    ///0x10 - FDCAN test register
67    #[inline(always)]
68    pub const fn test(&self) -> &TEST {
69        &self.test
70    }
71    ///0x14 - FDCAN RAM watchdog register
72    #[inline(always)]
73    pub const fn rwd(&self) -> &RWD {
74        &self.rwd
75    }
76    ///0x18 - FDCAN CC control register
77    #[inline(always)]
78    pub const fn cccr(&self) -> &CCCR {
79        &self.cccr
80    }
81    ///0x1c - FDCAN nominal bit timing and prescaler register
82    #[inline(always)]
83    pub const fn nbtp(&self) -> &NBTP {
84        &self.nbtp
85    }
86    ///0x20 - FDCAN timestamp counter configuration register
87    #[inline(always)]
88    pub const fn tscc(&self) -> &TSCC {
89        &self.tscc
90    }
91    ///0x24 - FDCAN timestamp counter value register
92    #[inline(always)]
93    pub const fn tscv(&self) -> &TSCV {
94        &self.tscv
95    }
96    ///0x28 - FDCAN timeout counter configuration register
97    #[inline(always)]
98    pub const fn tocc(&self) -> &TOCC {
99        &self.tocc
100    }
101    ///0x2c - FDCAN timeout counter value register
102    #[inline(always)]
103    pub const fn tocv(&self) -> &TOCV {
104        &self.tocv
105    }
106    ///0x40 - FDCAN error counter register
107    #[inline(always)]
108    pub const fn ecr(&self) -> &ECR {
109        &self.ecr
110    }
111    ///0x44 - FDCAN protocol status register
112    #[inline(always)]
113    pub const fn psr(&self) -> &PSR {
114        &self.psr
115    }
116    ///0x48 - FDCAN transmitter delay compensation register
117    #[inline(always)]
118    pub const fn tdcr(&self) -> &TDCR {
119        &self.tdcr
120    }
121    ///0x50 - FDCAN interrupt register
122    #[inline(always)]
123    pub const fn ir(&self) -> &IR {
124        &self.ir
125    }
126    ///0x54 - FDCAN interrupt enable register
127    #[inline(always)]
128    pub const fn ie(&self) -> &IE {
129        &self.ie
130    }
131    ///0x58 - FDCAN interrupt line select register
132    #[inline(always)]
133    pub const fn ils(&self) -> &ILS {
134        &self.ils
135    }
136    ///0x5c - FDCAN interrupt line enable register
137    #[inline(always)]
138    pub const fn ile(&self) -> &ILE {
139        &self.ile
140    }
141    ///0x80 - FDCAN global filter configuration register
142    #[inline(always)]
143    pub const fn rxgfc(&self) -> &RXGFC {
144        &self.rxgfc
145    }
146    ///0x84 - FDCAN extended ID and mask register
147    #[inline(always)]
148    pub const fn xidam(&self) -> &XIDAM {
149        &self.xidam
150    }
151    ///0x88 - FDCAN high-priority message status register
152    #[inline(always)]
153    pub const fn hpms(&self) -> &HPMS {
154        &self.hpms
155    }
156    ///0x90 - FDCAN Rx FIFO 0 status register
157    #[inline(always)]
158    pub const fn rxf0s(&self) -> &RXF0S {
159        &self.rxf0s
160    }
161    ///0x94 - CAN Rx FIFO 0 acknowledge register
162    #[inline(always)]
163    pub const fn rxf0a(&self) -> &RXF0A {
164        &self.rxf0a
165    }
166    ///0x98 - FDCAN Rx FIFO 1 status register
167    #[inline(always)]
168    pub const fn rxf1s(&self) -> &RXF1S {
169        &self.rxf1s
170    }
171    ///0x9c - FDCAN Rx FIFO 1 acknowledge register
172    #[inline(always)]
173    pub const fn rxf1a(&self) -> &RXF1A {
174        &self.rxf1a
175    }
176    ///0xc0 - FDCAN Tx buffer configuration register
177    #[inline(always)]
178    pub const fn txbc(&self) -> &TXBC {
179        &self.txbc
180    }
181    ///0xc4 - FDCAN Tx FIFO/queue status register
182    #[inline(always)]
183    pub const fn txfqs(&self) -> &TXFQS {
184        &self.txfqs
185    }
186    ///0xc8 - FDCAN Tx buffer request pending register
187    #[inline(always)]
188    pub const fn txbrp(&self) -> &TXBRP {
189        &self.txbrp
190    }
191    ///0xcc - FDCAN Tx buffer add request register
192    #[inline(always)]
193    pub const fn txbar(&self) -> &TXBAR {
194        &self.txbar
195    }
196    ///0xd0 - FDCAN Tx buffer cancellation request register
197    #[inline(always)]
198    pub const fn txbcr(&self) -> &TXBCR {
199        &self.txbcr
200    }
201    ///0xd4 - FDCAN Tx buffer transmission occurred register
202    #[inline(always)]
203    pub const fn txbto(&self) -> &TXBTO {
204        &self.txbto
205    }
206    ///0xd8 - FDCAN Tx buffer cancellation finished register
207    #[inline(always)]
208    pub const fn txbcf(&self) -> &TXBCF {
209        &self.txbcf
210    }
211    ///0xdc - FDCAN Tx buffer transmission interrupt enable register
212    #[inline(always)]
213    pub const fn txbtie(&self) -> &TXBTIE {
214        &self.txbtie
215    }
216    ///0xe0 - FDCAN Tx buffer cancellation finished interrupt enable register
217    #[inline(always)]
218    pub const fn txbcie(&self) -> &TXBCIE {
219        &self.txbcie
220    }
221    ///0xe4 - FDCAN Tx event FIFO status register
222    #[inline(always)]
223    pub const fn txefs(&self) -> &TXEFS {
224        &self.txefs
225    }
226    ///0xe8 - FDCAN Tx event FIFO acknowledge register
227    #[inline(always)]
228    pub const fn txefa(&self) -> &TXEFA {
229        &self.txefa
230    }
231    ///0x100 - FDCAN CFG clock divider register
232    #[inline(always)]
233    pub const fn ckdiv(&self) -> &CKDIV {
234        &self.ckdiv
235    }
236}
237/**CREL (r) register accessor: FDCAN core release register
238
239You can [`read`](crate::Reg::read) this register and get [`crel::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
240
241See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:CREL)
242
243For information about available fields see [`mod@crel`] module*/
244pub type CREL = crate::Reg<crel::CRELrs>;
245///FDCAN core release register
246pub mod crel;
247/**ENDN (r) register accessor: FDCAN endian register
248
249You can [`read`](crate::Reg::read) this register and get [`endn::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
250
251See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:ENDN)
252
253For information about available fields see [`mod@endn`] module*/
254pub type ENDN = crate::Reg<endn::ENDNrs>;
255///FDCAN endian register
256pub mod endn;
257/**DBTP (rw) register accessor: FDCAN data bit timing and prescaler register
258
259You can [`read`](crate::Reg::read) this register and get [`dbtp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbtp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
260
261See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:DBTP)
262
263For information about available fields see [`mod@dbtp`] module*/
264pub type DBTP = crate::Reg<dbtp::DBTPrs>;
265///FDCAN data bit timing and prescaler register
266pub mod dbtp;
267/**TEST (rw) register accessor: FDCAN test register
268
269You can [`read`](crate::Reg::read) this register and get [`test::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`test::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
270
271See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TEST)
272
273For information about available fields see [`mod@test`] module*/
274pub type TEST = crate::Reg<test::TESTrs>;
275///FDCAN test register
276pub mod test;
277/**RWD (rw) register accessor: FDCAN RAM watchdog register
278
279You can [`read`](crate::Reg::read) this register and get [`rwd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rwd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
280
281See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:RWD)
282
283For information about available fields see [`mod@rwd`] module*/
284pub type RWD = crate::Reg<rwd::RWDrs>;
285///FDCAN RAM watchdog register
286pub mod rwd;
287/**CCCR (rw) register accessor: FDCAN CC control register
288
289You can [`read`](crate::Reg::read) this register and get [`cccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
290
291See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:CCCR)
292
293For information about available fields see [`mod@cccr`] module*/
294pub type CCCR = crate::Reg<cccr::CCCRrs>;
295///FDCAN CC control register
296pub mod cccr;
297/**NBTP (rw) register accessor: FDCAN nominal bit timing and prescaler register
298
299You can [`read`](crate::Reg::read) this register and get [`nbtp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nbtp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
300
301See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:NBTP)
302
303For information about available fields see [`mod@nbtp`] module*/
304pub type NBTP = crate::Reg<nbtp::NBTPrs>;
305///FDCAN nominal bit timing and prescaler register
306pub mod nbtp;
307/**TSCC (rw) register accessor: FDCAN timestamp counter configuration register
308
309You can [`read`](crate::Reg::read) this register and get [`tscc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tscc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
310
311See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TSCC)
312
313For information about available fields see [`mod@tscc`] module*/
314pub type TSCC = crate::Reg<tscc::TSCCrs>;
315///FDCAN timestamp counter configuration register
316pub mod tscc;
317/**TSCV (rw) register accessor: FDCAN timestamp counter value register
318
319You can [`read`](crate::Reg::read) this register and get [`tscv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tscv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
320
321See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TSCV)
322
323For information about available fields see [`mod@tscv`] module*/
324pub type TSCV = crate::Reg<tscv::TSCVrs>;
325///FDCAN timestamp counter value register
326pub mod tscv;
327/**TOCC (rw) register accessor: FDCAN timeout counter configuration register
328
329You can [`read`](crate::Reg::read) this register and get [`tocc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tocc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
330
331See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TOCC)
332
333For information about available fields see [`mod@tocc`] module*/
334pub type TOCC = crate::Reg<tocc::TOCCrs>;
335///FDCAN timeout counter configuration register
336pub mod tocc;
337/**TOCV (rw) register accessor: FDCAN timeout counter value register
338
339You can [`read`](crate::Reg::read) this register and get [`tocv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tocv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
340
341See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TOCV)
342
343For information about available fields see [`mod@tocv`] module*/
344pub type TOCV = crate::Reg<tocv::TOCVrs>;
345///FDCAN timeout counter value register
346pub mod tocv;
347/**ECR (rw) register accessor: FDCAN error counter register
348
349You can [`read`](crate::Reg::read) this register and get [`ecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
350
351See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:ECR)
352
353For information about available fields see [`mod@ecr`] module*/
354pub type ECR = crate::Reg<ecr::ECRrs>;
355///FDCAN error counter register
356pub mod ecr;
357/**PSR (rw) register accessor: FDCAN protocol status register
358
359You can [`read`](crate::Reg::read) this register and get [`psr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
360
361See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:PSR)
362
363For information about available fields see [`mod@psr`] module*/
364pub type PSR = crate::Reg<psr::PSRrs>;
365///FDCAN protocol status register
366pub mod psr;
367/**TDCR (rw) register accessor: FDCAN transmitter delay compensation register
368
369You can [`read`](crate::Reg::read) this register and get [`tdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
370
371See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TDCR)
372
373For information about available fields see [`mod@tdcr`] module*/
374pub type TDCR = crate::Reg<tdcr::TDCRrs>;
375///FDCAN transmitter delay compensation register
376pub mod tdcr;
377/**IR (rw) register accessor: FDCAN interrupt register
378
379You can [`read`](crate::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
380
381See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:IR)
382
383For information about available fields see [`mod@ir`] module*/
384pub type IR = crate::Reg<ir::IRrs>;
385///FDCAN interrupt register
386pub mod ir;
387/**IE (rw) register accessor: FDCAN interrupt enable register
388
389You can [`read`](crate::Reg::read) this register and get [`ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
390
391See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:IE)
392
393For information about available fields see [`mod@ie`] module*/
394pub type IE = crate::Reg<ie::IErs>;
395///FDCAN interrupt enable register
396pub mod ie;
397/**ILS (rw) register accessor: FDCAN interrupt line select register
398
399You can [`read`](crate::Reg::read) this register and get [`ils::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ils::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
400
401See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:ILS)
402
403For information about available fields see [`mod@ils`] module*/
404pub type ILS = crate::Reg<ils::ILSrs>;
405///FDCAN interrupt line select register
406pub mod ils;
407/**ILE (rw) register accessor: FDCAN interrupt line enable register
408
409You can [`read`](crate::Reg::read) this register and get [`ile::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ile::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
410
411See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:ILE)
412
413For information about available fields see [`mod@ile`] module*/
414pub type ILE = crate::Reg<ile::ILErs>;
415///FDCAN interrupt line enable register
416pub mod ile;
417/**RXGFC (rw) register accessor: FDCAN global filter configuration register
418
419You can [`read`](crate::Reg::read) this register and get [`rxgfc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxgfc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
420
421See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:RXGFC)
422
423For information about available fields see [`mod@rxgfc`] module*/
424pub type RXGFC = crate::Reg<rxgfc::RXGFCrs>;
425///FDCAN global filter configuration register
426pub mod rxgfc;
427/**XIDAM (rw) register accessor: FDCAN extended ID and mask register
428
429You can [`read`](crate::Reg::read) this register and get [`xidam::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xidam::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
430
431See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:XIDAM)
432
433For information about available fields see [`mod@xidam`] module*/
434pub type XIDAM = crate::Reg<xidam::XIDAMrs>;
435///FDCAN extended ID and mask register
436pub mod xidam;
437/**HPMS (r) register accessor: FDCAN high-priority message status register
438
439You can [`read`](crate::Reg::read) this register and get [`hpms::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
440
441See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:HPMS)
442
443For information about available fields see [`mod@hpms`] module*/
444pub type HPMS = crate::Reg<hpms::HPMSrs>;
445///FDCAN high-priority message status register
446pub mod hpms;
447/**RXF0S (r) register accessor: FDCAN Rx FIFO 0 status register
448
449You can [`read`](crate::Reg::read) this register and get [`rxf0s::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
450
451See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:RXF0S)
452
453For information about available fields see [`mod@rxf0s`] module*/
454pub type RXF0S = crate::Reg<rxf0s::RXF0Srs>;
455///FDCAN Rx FIFO 0 status register
456pub mod rxf0s;
457/**RXF0A (rw) register accessor: CAN Rx FIFO 0 acknowledge register
458
459You can [`read`](crate::Reg::read) this register and get [`rxf0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
460
461See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:RXF0A)
462
463For information about available fields see [`mod@rxf0a`] module*/
464pub type RXF0A = crate::Reg<rxf0a::RXF0Ars>;
465///CAN Rx FIFO 0 acknowledge register
466pub mod rxf0a;
467/**RXF1S (r) register accessor: FDCAN Rx FIFO 1 status register
468
469You can [`read`](crate::Reg::read) this register and get [`rxf1s::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
470
471See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:RXF1S)
472
473For information about available fields see [`mod@rxf1s`] module*/
474pub type RXF1S = crate::Reg<rxf1s::RXF1Srs>;
475///FDCAN Rx FIFO 1 status register
476pub mod rxf1s;
477/**RXF1A (rw) register accessor: FDCAN Rx FIFO 1 acknowledge register
478
479You can [`read`](crate::Reg::read) this register and get [`rxf1a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf1a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
480
481See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:RXF1A)
482
483For information about available fields see [`mod@rxf1a`] module*/
484pub type RXF1A = crate::Reg<rxf1a::RXF1Ars>;
485///FDCAN Rx FIFO 1 acknowledge register
486pub mod rxf1a;
487/**TXBC (rw) register accessor: FDCAN Tx buffer configuration register
488
489You can [`read`](crate::Reg::read) this register and get [`txbc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
490
491See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXBC)
492
493For information about available fields see [`mod@txbc`] module*/
494pub type TXBC = crate::Reg<txbc::TXBCrs>;
495///FDCAN Tx buffer configuration register
496pub mod txbc;
497/**TXFQS (r) register accessor: FDCAN Tx FIFO/queue status register
498
499You can [`read`](crate::Reg::read) this register and get [`txfqs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
500
501See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXFQS)
502
503For information about available fields see [`mod@txfqs`] module*/
504pub type TXFQS = crate::Reg<txfqs::TXFQSrs>;
505///FDCAN Tx FIFO/queue status register
506pub mod txfqs;
507/**TXBRP (r) register accessor: FDCAN Tx buffer request pending register
508
509You can [`read`](crate::Reg::read) this register and get [`txbrp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
510
511See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXBRP)
512
513For information about available fields see [`mod@txbrp`] module*/
514pub type TXBRP = crate::Reg<txbrp::TXBRPrs>;
515///FDCAN Tx buffer request pending register
516pub mod txbrp;
517/**TXBAR (rw) register accessor: FDCAN Tx buffer add request register
518
519You can [`read`](crate::Reg::read) this register and get [`txbar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
520
521See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXBAR)
522
523For information about available fields see [`mod@txbar`] module*/
524pub type TXBAR = crate::Reg<txbar::TXBARrs>;
525///FDCAN Tx buffer add request register
526pub mod txbar;
527/**TXBCR (rw) register accessor: FDCAN Tx buffer cancellation request register
528
529You can [`read`](crate::Reg::read) this register and get [`txbcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
530
531See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXBCR)
532
533For information about available fields see [`mod@txbcr`] module*/
534pub type TXBCR = crate::Reg<txbcr::TXBCRrs>;
535///FDCAN Tx buffer cancellation request register
536pub mod txbcr;
537/**TXBTO (r) register accessor: FDCAN Tx buffer transmission occurred register
538
539You can [`read`](crate::Reg::read) this register and get [`txbto::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
540
541See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXBTO)
542
543For information about available fields see [`mod@txbto`] module*/
544pub type TXBTO = crate::Reg<txbto::TXBTOrs>;
545///FDCAN Tx buffer transmission occurred register
546pub mod txbto;
547/**TXBCF (r) register accessor: FDCAN Tx buffer cancellation finished register
548
549You can [`read`](crate::Reg::read) this register and get [`txbcf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
550
551See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXBCF)
552
553For information about available fields see [`mod@txbcf`] module*/
554pub type TXBCF = crate::Reg<txbcf::TXBCFrs>;
555///FDCAN Tx buffer cancellation finished register
556pub mod txbcf;
557/**TXBTIE (rw) register accessor: FDCAN Tx buffer transmission interrupt enable register
558
559You can [`read`](crate::Reg::read) this register and get [`txbtie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbtie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
560
561See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXBTIE)
562
563For information about available fields see [`mod@txbtie`] module*/
564pub type TXBTIE = crate::Reg<txbtie::TXBTIErs>;
565///FDCAN Tx buffer transmission interrupt enable register
566pub mod txbtie;
567/**TXBCIE (rw) register accessor: FDCAN Tx buffer cancellation finished interrupt enable register
568
569You can [`read`](crate::Reg::read) this register and get [`txbcie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbcie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
570
571See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXBCIE)
572
573For information about available fields see [`mod@txbcie`] module*/
574pub type TXBCIE = crate::Reg<txbcie::TXBCIErs>;
575///FDCAN Tx buffer cancellation finished interrupt enable register
576pub mod txbcie;
577/**TXEFS (r) register accessor: FDCAN Tx event FIFO status register
578
579You can [`read`](crate::Reg::read) this register and get [`txefs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
580
581See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXEFS)
582
583For information about available fields see [`mod@txefs`] module*/
584pub type TXEFS = crate::Reg<txefs::TXEFSrs>;
585///FDCAN Tx event FIFO status register
586pub mod txefs;
587/**TXEFA (rw) register accessor: FDCAN Tx event FIFO acknowledge register
588
589You can [`read`](crate::Reg::read) this register and get [`txefa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txefa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
590
591See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:TXEFA)
592
593For information about available fields see [`mod@txefa`] module*/
594pub type TXEFA = crate::Reg<txefa::TXEFArs>;
595///FDCAN Tx event FIFO acknowledge register
596pub mod txefa;
597/**CKDIV (rw) register accessor: FDCAN CFG clock divider register
598
599You can [`read`](crate::Reg::read) this register and get [`ckdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ckdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
600
601See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:CKDIV)
602
603For information about available fields see [`mod@ckdiv`] module*/
604pub type CKDIV = crate::Reg<ckdiv::CKDIVrs>;
605///FDCAN CFG clock divider register
606pub mod ckdiv;
stm32g0/stm32g0c1/fdcan1.rs

stm32g0/stm32g0c1/
fdcan1.rs
