stm32g0/stm32g0b0/tim1/
smcr.rs

1///Register `SMCR` reader
2pub type R = crate::R<SMCRrs>;
3///Register `SMCR` writer
4pub type W = crate::W<SMCRrs>;
5///Field `SMS` reader - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
6pub type SMS_R = crate::FieldReader;
7///Field `SMS` writer - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
8pub type SMS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9///Field `OCCS` reader - OCREF clear selection This bit is used to select the OCREF clear source.
10pub type OCCS_R = crate::BitReader;
11///Field `OCCS` writer - OCREF clear selection This bit is used to select the OCREF clear source.
12pub type OCCS_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `TS` reader - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
14pub type TS_R = crate::FieldReader;
15///Field `TS` writer - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
16pub type TS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17/**Master/slave mode
18
19Value on reset: 0*/
20#[cfg_attr(feature = "defmt", derive(defmt::Format))]
21#[derive(Clone, Copy, Debug, PartialEq, Eq)]
22pub enum MSM {
23    ///0: No action
24    NoSync = 0,
25    ///1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
26    Sync = 1,
27}
28impl From<MSM> for bool {
29    #[inline(always)]
30    fn from(variant: MSM) -> Self {
31        variant as u8 != 0
32    }
33}
34///Field `MSM` reader - Master/slave mode
35pub type MSM_R = crate::BitReader<MSM>;
36impl MSM_R {
37    ///Get enumerated values variant
38    #[inline(always)]
39    pub const fn variant(&self) -> MSM {
40        match self.bits {
41            false => MSM::NoSync,
42            true => MSM::Sync,
43        }
44    }
45    ///No action
46    #[inline(always)]
47    pub fn is_no_sync(&self) -> bool {
48        *self == MSM::NoSync
49    }
50    ///The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
51    #[inline(always)]
52    pub fn is_sync(&self) -> bool {
53        *self == MSM::Sync
54    }
55}
56///Field `MSM` writer - Master/slave mode
57pub type MSM_W<'a, REG> = crate::BitWriter<'a, REG, MSM>;
58impl<'a, REG> MSM_W<'a, REG>
59where
60    REG: crate::Writable + crate::RegisterSpec,
61{
62    ///No action
63    #[inline(always)]
64    pub fn no_sync(self) -> &'a mut crate::W<REG> {
65        self.variant(MSM::NoSync)
66    }
67    ///The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
68    #[inline(always)]
69    pub fn sync(self) -> &'a mut crate::W<REG> {
70        self.variant(MSM::Sync)
71    }
72}
73/**External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
74
75Value on reset: 0*/
76#[cfg_attr(feature = "defmt", derive(defmt::Format))]
77#[derive(Clone, Copy, Debug, PartialEq, Eq)]
78#[repr(u8)]
79pub enum ETF {
80    ///0: No filter, sampling is done at fDTS
81    NoFilter = 0,
82    ///1: fSAMPLING=fCK_INT, N=2
83    FckIntN2 = 1,
84    ///2: fSAMPLING=fCK_INT, N=4
85    FckIntN4 = 2,
86    ///3: fSAMPLING=fCK_INT, N=8
87    FckIntN8 = 3,
88    ///4: fSAMPLING=fDTS/2, N=6
89    FdtsDiv2N6 = 4,
90    ///5: fSAMPLING=fDTS/2, N=8
91    FdtsDiv2N8 = 5,
92    ///6: fSAMPLING=fDTS/4, N=6
93    FdtsDiv4N6 = 6,
94    ///7: fSAMPLING=fDTS/4, N=8
95    FdtsDiv4N8 = 7,
96    ///8: fSAMPLING=fDTS/8, N=6
97    FdtsDiv8N6 = 8,
98    ///9: fSAMPLING=fDTS/8, N=8
99    FdtsDiv8N8 = 9,
100    ///10: fSAMPLING=fDTS/16, N=5
101    FdtsDiv16N5 = 10,
102    ///11: fSAMPLING=fDTS/16, N=6
103    FdtsDiv16N6 = 11,
104    ///12: fSAMPLING=fDTS/16, N=8
105    FdtsDiv16N8 = 12,
106    ///13: fSAMPLING=fDTS/32, N=5
107    FdtsDiv32N5 = 13,
108    ///14: fSAMPLING=fDTS/32, N=6
109    FdtsDiv32N6 = 14,
110    ///15: fSAMPLING=fDTS/32, N=8
111    FdtsDiv32N8 = 15,
112}
113impl From<ETF> for u8 {
114    #[inline(always)]
115    fn from(variant: ETF) -> Self {
116        variant as _
117    }
118}
119impl crate::FieldSpec for ETF {
120    type Ux = u8;
121}
122impl crate::IsEnum for ETF {}
123///Field `ETF` reader - External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
124pub type ETF_R = crate::FieldReader<ETF>;
125impl ETF_R {
126    ///Get enumerated values variant
127    #[inline(always)]
128    pub const fn variant(&self) -> ETF {
129        match self.bits {
130            0 => ETF::NoFilter,
131            1 => ETF::FckIntN2,
132            2 => ETF::FckIntN4,
133            3 => ETF::FckIntN8,
134            4 => ETF::FdtsDiv2N6,
135            5 => ETF::FdtsDiv2N8,
136            6 => ETF::FdtsDiv4N6,
137            7 => ETF::FdtsDiv4N8,
138            8 => ETF::FdtsDiv8N6,
139            9 => ETF::FdtsDiv8N8,
140            10 => ETF::FdtsDiv16N5,
141            11 => ETF::FdtsDiv16N6,
142            12 => ETF::FdtsDiv16N8,
143            13 => ETF::FdtsDiv32N5,
144            14 => ETF::FdtsDiv32N6,
145            15 => ETF::FdtsDiv32N8,
146            _ => unreachable!(),
147        }
148    }
149    ///No filter, sampling is done at fDTS
150    #[inline(always)]
151    pub fn is_no_filter(&self) -> bool {
152        *self == ETF::NoFilter
153    }
154    ///fSAMPLING=fCK_INT, N=2
155    #[inline(always)]
156    pub fn is_fck_int_n2(&self) -> bool {
157        *self == ETF::FckIntN2
158    }
159    ///fSAMPLING=fCK_INT, N=4
160    #[inline(always)]
161    pub fn is_fck_int_n4(&self) -> bool {
162        *self == ETF::FckIntN4
163    }
164    ///fSAMPLING=fCK_INT, N=8
165    #[inline(always)]
166    pub fn is_fck_int_n8(&self) -> bool {
167        *self == ETF::FckIntN8
168    }
169    ///fSAMPLING=fDTS/2, N=6
170    #[inline(always)]
171    pub fn is_fdts_div2_n6(&self) -> bool {
172        *self == ETF::FdtsDiv2N6
173    }
174    ///fSAMPLING=fDTS/2, N=8
175    #[inline(always)]
176    pub fn is_fdts_div2_n8(&self) -> bool {
177        *self == ETF::FdtsDiv2N8
178    }
179    ///fSAMPLING=fDTS/4, N=6
180    #[inline(always)]
181    pub fn is_fdts_div4_n6(&self) -> bool {
182        *self == ETF::FdtsDiv4N6
183    }
184    ///fSAMPLING=fDTS/4, N=8
185    #[inline(always)]
186    pub fn is_fdts_div4_n8(&self) -> bool {
187        *self == ETF::FdtsDiv4N8
188    }
189    ///fSAMPLING=fDTS/8, N=6
190    #[inline(always)]
191    pub fn is_fdts_div8_n6(&self) -> bool {
192        *self == ETF::FdtsDiv8N6
193    }
194    ///fSAMPLING=fDTS/8, N=8
195    #[inline(always)]
196    pub fn is_fdts_div8_n8(&self) -> bool {
197        *self == ETF::FdtsDiv8N8
198    }
199    ///fSAMPLING=fDTS/16, N=5
200    #[inline(always)]
201    pub fn is_fdts_div16_n5(&self) -> bool {
202        *self == ETF::FdtsDiv16N5
203    }
204    ///fSAMPLING=fDTS/16, N=6
205    #[inline(always)]
206    pub fn is_fdts_div16_n6(&self) -> bool {
207        *self == ETF::FdtsDiv16N6
208    }
209    ///fSAMPLING=fDTS/16, N=8
210    #[inline(always)]
211    pub fn is_fdts_div16_n8(&self) -> bool {
212        *self == ETF::FdtsDiv16N8
213    }
214    ///fSAMPLING=fDTS/32, N=5
215    #[inline(always)]
216    pub fn is_fdts_div32_n5(&self) -> bool {
217        *self == ETF::FdtsDiv32N5
218    }
219    ///fSAMPLING=fDTS/32, N=6
220    #[inline(always)]
221    pub fn is_fdts_div32_n6(&self) -> bool {
222        *self == ETF::FdtsDiv32N6
223    }
224    ///fSAMPLING=fDTS/32, N=8
225    #[inline(always)]
226    pub fn is_fdts_div32_n8(&self) -> bool {
227        *self == ETF::FdtsDiv32N8
228    }
229}
230///Field `ETF` writer - External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
231pub type ETF_W<'a, REG> = crate::FieldWriter<'a, REG, 4, ETF, crate::Safe>;
232impl<'a, REG> ETF_W<'a, REG>
233where
234    REG: crate::Writable + crate::RegisterSpec,
235    REG::Ux: From<u8>,
236{
237    ///No filter, sampling is done at fDTS
238    #[inline(always)]
239    pub fn no_filter(self) -> &'a mut crate::W<REG> {
240        self.variant(ETF::NoFilter)
241    }
242    ///fSAMPLING=fCK_INT, N=2
243    #[inline(always)]
244    pub fn fck_int_n2(self) -> &'a mut crate::W<REG> {
245        self.variant(ETF::FckIntN2)
246    }
247    ///fSAMPLING=fCK_INT, N=4
248    #[inline(always)]
249    pub fn fck_int_n4(self) -> &'a mut crate::W<REG> {
250        self.variant(ETF::FckIntN4)
251    }
252    ///fSAMPLING=fCK_INT, N=8
253    #[inline(always)]
254    pub fn fck_int_n8(self) -> &'a mut crate::W<REG> {
255        self.variant(ETF::FckIntN8)
256    }
257    ///fSAMPLING=fDTS/2, N=6
258    #[inline(always)]
259    pub fn fdts_div2_n6(self) -> &'a mut crate::W<REG> {
260        self.variant(ETF::FdtsDiv2N6)
261    }
262    ///fSAMPLING=fDTS/2, N=8
263    #[inline(always)]
264    pub fn fdts_div2_n8(self) -> &'a mut crate::W<REG> {
265        self.variant(ETF::FdtsDiv2N8)
266    }
267    ///fSAMPLING=fDTS/4, N=6
268    #[inline(always)]
269    pub fn fdts_div4_n6(self) -> &'a mut crate::W<REG> {
270        self.variant(ETF::FdtsDiv4N6)
271    }
272    ///fSAMPLING=fDTS/4, N=8
273    #[inline(always)]
274    pub fn fdts_div4_n8(self) -> &'a mut crate::W<REG> {
275        self.variant(ETF::FdtsDiv4N8)
276    }
277    ///fSAMPLING=fDTS/8, N=6
278    #[inline(always)]
279    pub fn fdts_div8_n6(self) -> &'a mut crate::W<REG> {
280        self.variant(ETF::FdtsDiv8N6)
281    }
282    ///fSAMPLING=fDTS/8, N=8
283    #[inline(always)]
284    pub fn fdts_div8_n8(self) -> &'a mut crate::W<REG> {
285        self.variant(ETF::FdtsDiv8N8)
286    }
287    ///fSAMPLING=fDTS/16, N=5
288    #[inline(always)]
289    pub fn fdts_div16_n5(self) -> &'a mut crate::W<REG> {
290        self.variant(ETF::FdtsDiv16N5)
291    }
292    ///fSAMPLING=fDTS/16, N=6
293    #[inline(always)]
294    pub fn fdts_div16_n6(self) -> &'a mut crate::W<REG> {
295        self.variant(ETF::FdtsDiv16N6)
296    }
297    ///fSAMPLING=fDTS/16, N=8
298    #[inline(always)]
299    pub fn fdts_div16_n8(self) -> &'a mut crate::W<REG> {
300        self.variant(ETF::FdtsDiv16N8)
301    }
302    ///fSAMPLING=fDTS/32, N=5
303    #[inline(always)]
304    pub fn fdts_div32_n5(self) -> &'a mut crate::W<REG> {
305        self.variant(ETF::FdtsDiv32N5)
306    }
307    ///fSAMPLING=fDTS/32, N=6
308    #[inline(always)]
309    pub fn fdts_div32_n6(self) -> &'a mut crate::W<REG> {
310        self.variant(ETF::FdtsDiv32N6)
311    }
312    ///fSAMPLING=fDTS/32, N=8
313    #[inline(always)]
314    pub fn fdts_div32_n8(self) -> &'a mut crate::W<REG> {
315        self.variant(ETF::FdtsDiv32N8)
316    }
317}
318/**External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
319
320Value on reset: 0*/
321#[cfg_attr(feature = "defmt", derive(defmt::Format))]
322#[derive(Clone, Copy, Debug, PartialEq, Eq)]
323#[repr(u8)]
324pub enum ETPS {
325    ///0: Prescaler OFF
326    Div1 = 0,
327    ///1: ETRP frequency divided by 2
328    Div2 = 1,
329    ///2: ETRP frequency divided by 4
330    Div4 = 2,
331    ///3: ETRP frequency divided by 8
332    Div8 = 3,
333}
334impl From<ETPS> for u8 {
335    #[inline(always)]
336    fn from(variant: ETPS) -> Self {
337        variant as _
338    }
339}
340impl crate::FieldSpec for ETPS {
341    type Ux = u8;
342}
343impl crate::IsEnum for ETPS {}
344///Field `ETPS` reader - External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
345pub type ETPS_R = crate::FieldReader<ETPS>;
346impl ETPS_R {
347    ///Get enumerated values variant
348    #[inline(always)]
349    pub const fn variant(&self) -> ETPS {
350        match self.bits {
351            0 => ETPS::Div1,
352            1 => ETPS::Div2,
353            2 => ETPS::Div4,
354            3 => ETPS::Div8,
355            _ => unreachable!(),
356        }
357    }
358    ///Prescaler OFF
359    #[inline(always)]
360    pub fn is_div1(&self) -> bool {
361        *self == ETPS::Div1
362    }
363    ///ETRP frequency divided by 2
364    #[inline(always)]
365    pub fn is_div2(&self) -> bool {
366        *self == ETPS::Div2
367    }
368    ///ETRP frequency divided by 4
369    #[inline(always)]
370    pub fn is_div4(&self) -> bool {
371        *self == ETPS::Div4
372    }
373    ///ETRP frequency divided by 8
374    #[inline(always)]
375    pub fn is_div8(&self) -> bool {
376        *self == ETPS::Div8
377    }
378}
379///Field `ETPS` writer - External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
380pub type ETPS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ETPS, crate::Safe>;
381impl<'a, REG> ETPS_W<'a, REG>
382where
383    REG: crate::Writable + crate::RegisterSpec,
384    REG::Ux: From<u8>,
385{
386    ///Prescaler OFF
387    #[inline(always)]
388    pub fn div1(self) -> &'a mut crate::W<REG> {
389        self.variant(ETPS::Div1)
390    }
391    ///ETRP frequency divided by 2
392    #[inline(always)]
393    pub fn div2(self) -> &'a mut crate::W<REG> {
394        self.variant(ETPS::Div2)
395    }
396    ///ETRP frequency divided by 4
397    #[inline(always)]
398    pub fn div4(self) -> &'a mut crate::W<REG> {
399        self.variant(ETPS::Div4)
400    }
401    ///ETRP frequency divided by 8
402    #[inline(always)]
403    pub fn div8(self) -> &'a mut crate::W<REG> {
404        self.variant(ETPS::Div8)
405    }
406}
407/**External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
408
409Value on reset: 0*/
410#[cfg_attr(feature = "defmt", derive(defmt::Format))]
411#[derive(Clone, Copy, Debug, PartialEq, Eq)]
412pub enum ECE {
413    ///0: External clock mode 2 disabled
414    Disabled = 0,
415    ///1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
416    Enabled = 1,
417}
418impl From<ECE> for bool {
419    #[inline(always)]
420    fn from(variant: ECE) -> Self {
421        variant as u8 != 0
422    }
423}
424///Field `ECE` reader - External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
425pub type ECE_R = crate::BitReader<ECE>;
426impl ECE_R {
427    ///Get enumerated values variant
428    #[inline(always)]
429    pub const fn variant(&self) -> ECE {
430        match self.bits {
431            false => ECE::Disabled,
432            true => ECE::Enabled,
433        }
434    }
435    ///External clock mode 2 disabled
436    #[inline(always)]
437    pub fn is_disabled(&self) -> bool {
438        *self == ECE::Disabled
439    }
440    ///External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
441    #[inline(always)]
442    pub fn is_enabled(&self) -> bool {
443        *self == ECE::Enabled
444    }
445}
446///Field `ECE` writer - External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
447pub type ECE_W<'a, REG> = crate::BitWriter<'a, REG, ECE>;
448impl<'a, REG> ECE_W<'a, REG>
449where
450    REG: crate::Writable + crate::RegisterSpec,
451{
452    ///External clock mode 2 disabled
453    #[inline(always)]
454    pub fn disabled(self) -> &'a mut crate::W<REG> {
455        self.variant(ECE::Disabled)
456    }
457    ///External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
458    #[inline(always)]
459    pub fn enabled(self) -> &'a mut crate::W<REG> {
460        self.variant(ECE::Enabled)
461    }
462}
463/**External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
464
465Value on reset: 0*/
466#[cfg_attr(feature = "defmt", derive(defmt::Format))]
467#[derive(Clone, Copy, Debug, PartialEq, Eq)]
468pub enum ETP {
469    ///0: ETR is noninverted, active at high level or rising edge
470    NotInverted = 0,
471    ///1: ETR is inverted, active at low level or falling edge
472    Inverted = 1,
473}
474impl From<ETP> for bool {
475    #[inline(always)]
476    fn from(variant: ETP) -> Self {
477        variant as u8 != 0
478    }
479}
480///Field `ETP` reader - External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
481pub type ETP_R = crate::BitReader<ETP>;
482impl ETP_R {
483    ///Get enumerated values variant
484    #[inline(always)]
485    pub const fn variant(&self) -> ETP {
486        match self.bits {
487            false => ETP::NotInverted,
488            true => ETP::Inverted,
489        }
490    }
491    ///ETR is noninverted, active at high level or rising edge
492    #[inline(always)]
493    pub fn is_not_inverted(&self) -> bool {
494        *self == ETP::NotInverted
495    }
496    ///ETR is inverted, active at low level or falling edge
497    #[inline(always)]
498    pub fn is_inverted(&self) -> bool {
499        *self == ETP::Inverted
500    }
501}
502///Field `ETP` writer - External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
503pub type ETP_W<'a, REG> = crate::BitWriter<'a, REG, ETP>;
504impl<'a, REG> ETP_W<'a, REG>
505where
506    REG: crate::Writable + crate::RegisterSpec,
507{
508    ///ETR is noninverted, active at high level or rising edge
509    #[inline(always)]
510    pub fn not_inverted(self) -> &'a mut crate::W<REG> {
511        self.variant(ETP::NotInverted)
512    }
513    ///ETR is inverted, active at low level or falling edge
514    #[inline(always)]
515    pub fn inverted(self) -> &'a mut crate::W<REG> {
516        self.variant(ETP::Inverted)
517    }
518}
519///Field `SMS_3` reader - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
520pub type SMS_3_R = crate::BitReader;
521///Field `SMS_3` writer - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
522pub type SMS_3_W<'a, REG> = crate::BitWriter<'a, REG>;
523///Field `TS2` reader - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
524pub type TS2_R = crate::FieldReader;
525///Field `TS2` writer - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
526pub type TS2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
527impl R {
528    ///Bits 0:2 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
529    #[inline(always)]
530    pub fn sms(&self) -> SMS_R {
531        SMS_R::new((self.bits & 7) as u8)
532    }
533    ///Bit 3 - OCREF clear selection This bit is used to select the OCREF clear source.
534    #[inline(always)]
535    pub fn occs(&self) -> OCCS_R {
536        OCCS_R::new(((self.bits >> 3) & 1) != 0)
537    }
538    ///Bits 4:6 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
539    #[inline(always)]
540    pub fn ts(&self) -> TS_R {
541        TS_R::new(((self.bits >> 4) & 7) as u8)
542    }
543    ///Bit 7 - Master/slave mode
544    #[inline(always)]
545    pub fn msm(&self) -> MSM_R {
546        MSM_R::new(((self.bits >> 7) & 1) != 0)
547    }
548    ///Bits 8:11 - External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
549    #[inline(always)]
550    pub fn etf(&self) -> ETF_R {
551        ETF_R::new(((self.bits >> 8) & 0x0f) as u8)
552    }
553    ///Bits 12:13 - External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
554    #[inline(always)]
555    pub fn etps(&self) -> ETPS_R {
556        ETPS_R::new(((self.bits >> 12) & 3) as u8)
557    }
558    ///Bit 14 - External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
559    #[inline(always)]
560    pub fn ece(&self) -> ECE_R {
561        ECE_R::new(((self.bits >> 14) & 1) != 0)
562    }
563    ///Bit 15 - External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
564    #[inline(always)]
565    pub fn etp(&self) -> ETP_R {
566        ETP_R::new(((self.bits >> 15) & 1) != 0)
567    }
568    ///Bit 16 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
569    #[inline(always)]
570    pub fn sms_3(&self) -> SMS_3_R {
571        SMS_3_R::new(((self.bits >> 16) & 1) != 0)
572    }
573    ///Bits 20:21 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
574    #[inline(always)]
575    pub fn ts2(&self) -> TS2_R {
576        TS2_R::new(((self.bits >> 20) & 3) as u8)
577    }
578}
579impl core::fmt::Debug for R {
580    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
581        f.debug_struct("SMCR")
582            .field("sms", &self.sms())
583            .field("occs", &self.occs())
584            .field("ts", &self.ts())
585            .field("msm", &self.msm())
586            .field("etf", &self.etf())
587            .field("etps", &self.etps())
588            .field("ece", &self.ece())
589            .field("etp", &self.etp())
590            .field("sms_3", &self.sms_3())
591            .field("ts2", &self.ts2())
592            .finish()
593    }
594}
595impl W {
596    ///Bits 0:2 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
597    #[inline(always)]
598    pub fn sms(&mut self) -> SMS_W<SMCRrs> {
599        SMS_W::new(self, 0)
600    }
601    ///Bit 3 - OCREF clear selection This bit is used to select the OCREF clear source.
602    #[inline(always)]
603    pub fn occs(&mut self) -> OCCS_W<SMCRrs> {
604        OCCS_W::new(self, 3)
605    }
606    ///Bits 4:6 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
607    #[inline(always)]
608    pub fn ts(&mut self) -> TS_W<SMCRrs> {
609        TS_W::new(self, 4)
610    }
611    ///Bit 7 - Master/slave mode
612    #[inline(always)]
613    pub fn msm(&mut self) -> MSM_W<SMCRrs> {
614        MSM_W::new(self, 7)
615    }
616    ///Bits 8:11 - External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
617    #[inline(always)]
618    pub fn etf(&mut self) -> ETF_W<SMCRrs> {
619        ETF_W::new(self, 8)
620    }
621    ///Bits 12:13 - External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
622    #[inline(always)]
623    pub fn etps(&mut self) -> ETPS_W<SMCRrs> {
624        ETPS_W::new(self, 12)
625    }
626    ///Bit 14 - External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
627    #[inline(always)]
628    pub fn ece(&mut self) -> ECE_W<SMCRrs> {
629        ECE_W::new(self, 14)
630    }
631    ///Bit 15 - External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
632    #[inline(always)]
633    pub fn etp(&mut self) -> ETP_W<SMCRrs> {
634        ETP_W::new(self, 15)
635    }
636    ///Bit 16 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
637    #[inline(always)]
638    pub fn sms_3(&mut self) -> SMS_3_W<SMCRrs> {
639        SMS_3_W::new(self, 16)
640    }
641    ///Bits 20:21 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
642    #[inline(always)]
643    pub fn ts2(&mut self) -> TS2_W<SMCRrs> {
644        TS2_W::new(self, 20)
645    }
646}
647/**slave mode control register
648
649You can [`read`](crate::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
650
651See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM1:SMCR)*/
652pub struct SMCRrs;
653impl crate::RegisterSpec for SMCRrs {
654    type Ux = u32;
655}
656///`read()` method returns [`smcr::R`](R) reader structure
657impl crate::Readable for SMCRrs {}
658///`write(|w| ..)` method takes [`smcr::W`](W) writer structure
659impl crate::Writable for SMCRrs {
660    type Safety = crate::Unsafe;
661}
662///`reset()` method sets SMCR to value 0
663impl crate::Resettable for SMCRrs {}
stm32g0/stm32g0b0/tim1/smcr.rs

stm32g0/stm32g0b0/tim1/
smcr.rs
