stm32g0/stm32g081/rcc/
icscr.rs

1///Register `ICSCR` reader
2pub type R = crate::R<ICSCRrs>;
3///Register `ICSCR` writer
4pub type W = crate::W<ICSCRrs>;
5///Field `HSICAL` reader - HSI16 clock calibration
6pub type HSICAL_R = crate::FieldReader;
7///Field `HSITRIM` reader - HSI16 clock trimming
8pub type HSITRIM_R = crate::FieldReader;
9///Field `HSITRIM` writer - HSI16 clock trimming
10pub type HSITRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
11impl R {
12    ///Bits 0:7 - HSI16 clock calibration
13    #[inline(always)]
14    pub fn hsical(&self) -> HSICAL_R {
15        HSICAL_R::new((self.bits & 0xff) as u8)
16    }
17    ///Bits 8:14 - HSI16 clock trimming
18    #[inline(always)]
19    pub fn hsitrim(&self) -> HSITRIM_R {
20        HSITRIM_R::new(((self.bits >> 8) & 0x7f) as u8)
21    }
22}
23impl core::fmt::Debug for R {
24    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
25        f.debug_struct("ICSCR")
26            .field("hsical", &self.hsical())
27            .field("hsitrim", &self.hsitrim())
28            .finish()
29    }
30}
31impl W {
32    ///Bits 8:14 - HSI16 clock trimming
33    #[inline(always)]
34    pub fn hsitrim(&mut self) -> HSITRIM_W<ICSCRrs> {
35        HSITRIM_W::new(self, 8)
36    }
37}
38/**Internal clock sources calibration register
39
40You can [`read`](crate::Reg::read) this register and get [`icscr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icscr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
41
42See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RCC:ICSCR)*/
43pub struct ICSCRrs;
44impl crate::RegisterSpec for ICSCRrs {
45    type Ux = u32;
46}
47///`read()` method returns [`icscr::R`](R) reader structure
48impl crate::Readable for ICSCRrs {}
49///`write(|w| ..)` method takes [`icscr::W`](W) writer structure
50impl crate::Writable for ICSCRrs {
51    type Safety = crate::Unsafe;
52}
53///`reset()` method sets ICSCR to value 0x1000_0000
54impl crate::Resettable for ICSCRrs {
55    const RESET_VALUE: u32 = 0x1000_0000;
56}
stm32g0/stm32g081/rcc/icscr.rs

stm32g0/stm32g081/rcc/
icscr.rs
