stm32g0/stm32g070/spi1/
hwcfgr.rs

1///Register `HWCFGR` reader
2pub type R = crate::R<HWCFGRrs>;
3///Field `CRCCFG` reader - CRC capable at SPI mode
4pub type CRCCFG_R = crate::FieldReader;
5///Field `I2SCFG` reader - I2S mode implementation
6pub type I2SCFG_R = crate::FieldReader;
7///Field `I2SCKCFG` reader - I2S master clock generator at I2S mode
8pub type I2SCKCFG_R = crate::FieldReader;
9///Field `DSCFG` reader - SPI data size configuration
10pub type DSCFG_R = crate::FieldReader;
11///Field `NSSCFG` reader - NSS pulse feature enhancement at SPI master
12pub type NSSCFG_R = crate::FieldReader;
13impl R {
14    ///Bits 0:3 - CRC capable at SPI mode
15    #[inline(always)]
16    pub fn crccfg(&self) -> CRCCFG_R {
17        CRCCFG_R::new((self.bits & 0x0f) as u8)
18    }
19    ///Bits 4:7 - I2S mode implementation
20    #[inline(always)]
21    pub fn i2scfg(&self) -> I2SCFG_R {
22        I2SCFG_R::new(((self.bits >> 4) & 0x0f) as u8)
23    }
24    ///Bits 8:11 - I2S master clock generator at I2S mode
25    #[inline(always)]
26    pub fn i2sckcfg(&self) -> I2SCKCFG_R {
27        I2SCKCFG_R::new(((self.bits >> 8) & 0x0f) as u8)
28    }
29    ///Bits 12:15 - SPI data size configuration
30    #[inline(always)]
31    pub fn dscfg(&self) -> DSCFG_R {
32        DSCFG_R::new(((self.bits >> 12) & 0x0f) as u8)
33    }
34    ///Bits 16:19 - NSS pulse feature enhancement at SPI master
35    #[inline(always)]
36    pub fn nsscfg(&self) -> NSSCFG_R {
37        NSSCFG_R::new(((self.bits >> 16) & 0x0f) as u8)
38    }
39}
40impl core::fmt::Debug for R {
41    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
42        f.debug_struct("HWCFGR")
43            .field("crccfg", &self.crccfg())
44            .field("i2scfg", &self.i2scfg())
45            .field("i2sckcfg", &self.i2sckcfg())
46            .field("dscfg", &self.dscfg())
47            .field("nsscfg", &self.nsscfg())
48            .finish()
49    }
50}
51/**hardware configuration register
52
53You can [`read`](crate::Reg::read) this register and get [`hwcfgr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
54
55See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G070.html#SPI1:HWCFGR)*/
56pub struct HWCFGRrs;
57impl crate::RegisterSpec for HWCFGRrs {
58    type Ux = u32;
59}
60///`read()` method returns [`hwcfgr::R`](R) reader structure
61impl crate::Readable for HWCFGRrs {}
62///`reset()` method sets HWCFGR to value 0
63impl crate::Resettable for HWCFGRrs {}
stm32g0/stm32g070/spi1/hwcfgr.rs

stm32g0/stm32g070/spi1/
hwcfgr.rs
