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#[doc = r" Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - DAC control register"] pub dac_cr: DAC_CR, #[doc = "0x04 - DAC software trigger register"] pub dac_swtrgr: DAC_SWTRGR, #[doc = "0x08 - DAC channel1 12-bit right-aligned data holding register"] pub dac_dhr12r1: DAC_DHR12R1, #[doc = "0x0c - DAC channel1 12-bit left aligned data holding register"] pub dac_dhr12l1: DAC_DHR12L1, #[doc = "0x10 - DAC channel1 8-bit right aligned data holding register"] pub dac_dhr8r1: DAC_DHR8R1, #[doc = "0x14 - DAC channel2 12-bit right aligned data holding register"] pub dac_dhr12r2: DAC_DHR12R2, #[doc = "0x18 - DAC channel2 12-bit left aligned data holding register"] pub dac_dhr12l2: DAC_DHR12L2, #[doc = "0x1c - DAC channel2 8-bit right-aligned data holding register"] pub dac_dhr8r2: DAC_DHR8R2, #[doc = "0x20 - Dual DAC 12-bit right-aligned data holding register"] pub dac_dhr12rd: DAC_DHR12RD, #[doc = "0x24 - DUAL DAC 12-bit left aligned data holding register"] pub dac_dhr12ld: DAC_DHR12LD, #[doc = "0x28 - DUAL DAC 8-bit right aligned data holding register"] pub dac_dhr8rd: DAC_DHR8RD, #[doc = "0x2c - DAC channel1 data output register"] pub dac_dor1: DAC_DOR1, #[doc = "0x30 - DAC channel2 data output register"] pub dac_dor2: DAC_DOR2, #[doc = "0x34 - DAC status register"] pub dac_sr: DAC_SR, #[doc = "0x38 - DAC calibration control register"] pub dac_ccr: DAC_CCR, #[doc = "0x3c - DAC mode control register"] pub dac_mcr: DAC_MCR, #[doc = "0x40 - DAC Sample and Hold sample time register 1"] pub dac_shsr1: DAC_SHSR1, #[doc = "0x44 - DAC Sample and Hold sample time register 2"] pub dac_shsr2: DAC_SHSR2, #[doc = "0x48 - DAC Sample and Hold hold time register"] pub dac_shhr: DAC_SHHR, #[doc = "0x4c - DAC Sample and Hold refresh time register"] pub dac_shrr: DAC_SHRR, _reserved0: [u8; 928usize], #[doc = "0x3f0 - DAC IP Hardware Configuration Register"] pub ip_hwcfgr0: IP_HWCFGR0, #[doc = "0x3f4 - EXTI IP Version register"] pub verr: VERR, #[doc = "0x3f8 - EXTI Identification register"] pub ipidr: IPIDR, #[doc = "0x3fc - EXTI Size ID register"] pub sidr: SIDR, } #[doc = "DAC control register"] pub struct DAC_CR { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC control register"] pub mod dac_cr; #[doc = "DAC software trigger register"] pub struct DAC_SWTRGR { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC software trigger register"] pub mod dac_swtrgr; #[doc = "DAC channel1 12-bit right-aligned data holding register"] pub struct DAC_DHR12R1 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC channel1 12-bit right-aligned data holding register"] pub mod dac_dhr12r1; #[doc = "DAC channel1 12-bit left aligned data holding register"] pub struct DAC_DHR12L1 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC channel1 12-bit left aligned data holding register"] pub mod dac_dhr12l1; #[doc = "DAC channel1 8-bit right aligned data holding register"] pub struct DAC_DHR8R1 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC channel1 8-bit right aligned data holding register"] pub mod dac_dhr8r1; #[doc = "DAC channel2 12-bit right aligned data holding register"] pub struct DAC_DHR12R2 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC channel2 12-bit right aligned data holding register"] pub mod dac_dhr12r2; #[doc = "DAC channel2 12-bit left aligned data holding register"] pub struct DAC_DHR12L2 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC channel2 12-bit left aligned data holding register"] pub mod dac_dhr12l2; #[doc = "DAC channel2 8-bit right-aligned data holding register"] pub struct DAC_DHR8R2 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC channel2 8-bit right-aligned data holding register"] pub mod dac_dhr8r2; #[doc = "Dual DAC 12-bit right-aligned data holding register"] pub struct DAC_DHR12RD { register: ::vcell::VolatileCell<u32>, } #[doc = "Dual DAC 12-bit right-aligned data holding register"] pub mod dac_dhr12rd; #[doc = "DUAL DAC 12-bit left aligned data holding register"] pub struct DAC_DHR12LD { register: ::vcell::VolatileCell<u32>, } #[doc = "DUAL DAC 12-bit left aligned data holding register"] pub mod dac_dhr12ld; #[doc = "DUAL DAC 8-bit right aligned data holding register"] pub struct DAC_DHR8RD { register: ::vcell::VolatileCell<u32>, } #[doc = "DUAL DAC 8-bit right aligned data holding register"] pub mod dac_dhr8rd; #[doc = "DAC channel1 data output register"] pub struct DAC_DOR1 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC channel1 data output register"] pub mod dac_dor1; #[doc = "DAC channel2 data output register"] pub struct DAC_DOR2 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC channel2 data output register"] pub mod dac_dor2; #[doc = "DAC status register"] pub struct DAC_SR { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC status register"] pub mod dac_sr; #[doc = "DAC calibration control register"] pub struct DAC_CCR { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC calibration control register"] pub mod dac_ccr; #[doc = "DAC mode control register"] pub struct DAC_MCR { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC mode control register"] pub mod dac_mcr; #[doc = "DAC Sample and Hold sample time register 1"] pub struct DAC_SHSR1 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC Sample and Hold sample time register 1"] pub mod dac_shsr1; #[doc = "DAC Sample and Hold sample time register 2"] pub struct DAC_SHSR2 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC Sample and Hold sample time register 2"] pub mod dac_shsr2; #[doc = "DAC Sample and Hold hold time register"] pub struct DAC_SHHR { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC Sample and Hold hold time register"] pub mod dac_shhr; #[doc = "DAC Sample and Hold refresh time register"] pub struct DAC_SHRR { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC Sample and Hold refresh time register"] pub mod dac_shrr; #[doc = "DAC IP Hardware Configuration Register"] pub struct IP_HWCFGR0 { register: ::vcell::VolatileCell<u32>, } #[doc = "DAC IP Hardware Configuration Register"] pub mod ip_hwcfgr0; #[doc = "EXTI IP Version register"] pub struct VERR { register: ::vcell::VolatileCell<u32>, } #[doc = "EXTI IP Version register"] pub mod verr; #[doc = "EXTI Identification register"] pub struct IPIDR { register: ::vcell::VolatileCell<u32>, } #[doc = "EXTI Identification register"] pub mod ipidr; #[doc = "EXTI Size ID register"] pub struct SIDR { register: ::vcell::VolatileCell<u32>, } #[doc = "EXTI Size ID register"] pub mod sidr;