1#[doc = "Register `CR` reader"]
2pub struct R(crate::R<CR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CR` writer"]
17pub struct W(crate::W<CR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TXMODE` reader - Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the \"tBISTContMode\" delay), disable the peripheral (UCPDEN = 0)."]
38pub type TXMODE_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `TXMODE` writer - Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the \"tBISTContMode\" delay), disable the peripheral (UCPDEN = 0)."]
40pub type TXMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
41#[doc = "Field `TXSEND` reader - Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded."]
42pub type TXSEND_R = crate::BitReader<bool>;
43#[doc = "Field `TXSEND` writer - Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded."]
44pub type TXSEND_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
45#[doc = "Field `TXHRST` reader - Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded."]
46pub type TXHRST_R = crate::BitReader<bool>;
47#[doc = "Field `TXHRST` writer - Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded."]
48pub type TXHRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
49#[doc = "Field `RXMODE` reader - Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message."]
50pub type RXMODE_R = crate::BitReader<bool>;
51#[doc = "Field `RXMODE` writer - Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message."]
52pub type RXMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
53#[doc = "Field `PHYRXEN` reader - USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set."]
54pub type PHYRXEN_R = crate::BitReader<bool>;
55#[doc = "Field `PHYRXEN` writer - USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set."]
56pub type PHYRXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
57#[doc = "Field `PHYCCSEL` reader - CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach."]
58pub type PHYCCSEL_R = crate::BitReader<bool>;
59#[doc = "Field `PHYCCSEL` writer - CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach."]
60pub type PHYCCSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
61#[doc = "Field `ANASUBMODE` reader - Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield."]
62pub type ANASUBMODE_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `ANASUBMODE` writer - Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield."]
64pub type ANASUBMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
65#[doc = "Field `ANAMODE` reader - Analog PHY operating mode The bit takes effect upon setting the UCPDx_STROBE bit of the SYS_CONFIG register. The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE\\[1:0\\]."]
66pub type ANAMODE_R = crate::BitReader<bool>;
67#[doc = "Field `ANAMODE` writer - Analog PHY operating mode The bit takes effect upon setting the UCPDx_STROBE bit of the SYS_CONFIG register. The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE\\[1:0\\]."]
68pub type ANAMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
69#[doc = "Field `CCENABLE` reader - CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE\\[1:0\\]
70setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source."]
71pub type CCENABLE_R = crate::FieldReader<u8, u8>;
72#[doc = "Field `CCENABLE` writer - CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE\\[1:0\\]
73setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source."]
74pub type CCENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
75#[doc = "Field `CC1VCONNEN` reader - VCONN switch enable for CC1"]
76pub type CC1VCONNEN_R = crate::BitReader<bool>;
77#[doc = "Field `CC1VCONNEN` writer - VCONN switch enable for CC1"]
78pub type CC1VCONNEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
79#[doc = "Field `CC2VCONNEN` reader - VCONN switch enable for CC2"]
80pub type CC2VCONNEN_R = crate::BitReader<bool>;
81#[doc = "Field `CC2VCONNEN` writer - VCONN switch enable for CC2"]
82pub type CC2VCONNEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
83#[doc = "Field `DBATTEN` reader - Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured."]
84pub type DBATTEN_R = crate::BitReader<bool>;
85#[doc = "Field `DBATTEN` writer - Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured."]
86pub type DBATTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
87#[doc = "Field `FRSRXEN` reader - FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink."]
88pub type FRSRXEN_R = crate::BitReader<bool>;
89#[doc = "Field `FRSRXEN` writer - FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink."]
90pub type FRSRXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
91#[doc = "Field `FRSTX` reader - FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0."]
92pub type FRSTX_R = crate::BitReader<bool>;
93#[doc = "Field `FRSTX` writer - FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0."]
94pub type FRSTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
95#[doc = "Field `RDCH` reader - Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to \"USB Type-C ECN for Source VCONN Discharge\". The CCENABLE\\[1:0\\]
96bitfield must be set accordingly, too. Changing the bit value only takes effect upon setting the UCPDx_STROBE bit of the SYSCFG_CFGR1 register."]
97pub type RDCH_R = crate::BitReader<bool>;
98#[doc = "Field `RDCH` writer - Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to \"USB Type-C ECN for Source VCONN Discharge\". The CCENABLE\\[1:0\\]
99bitfield must be set accordingly, too. Changing the bit value only takes effect upon setting the UCPDx_STROBE bit of the SYSCFG_CFGR1 register."]
100pub type RDCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
101#[doc = "Field `CC1TCDIS` reader - CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
102pub type CC1TCDIS_R = crate::BitReader<bool>;
103#[doc = "Field `CC1TCDIS` writer - CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
104pub type CC1TCDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
105#[doc = "Field `CC2TCDIS` reader - CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
106pub type CC2TCDIS_R = crate::BitReader<bool>;
107#[doc = "Field `CC2TCDIS` writer - CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
108pub type CC2TCDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
109impl R {
110 #[doc = "Bits 0:1 - Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the \"tBISTContMode\" delay), disable the peripheral (UCPDEN = 0)."]
111 #[inline(always)]
112 pub fn txmode(&self) -> TXMODE_R {
113 TXMODE_R::new((self.bits & 3) as u8)
114 }
115 #[doc = "Bit 2 - Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded."]
116 #[inline(always)]
117 pub fn txsend(&self) -> TXSEND_R {
118 TXSEND_R::new(((self.bits >> 2) & 1) != 0)
119 }
120 #[doc = "Bit 3 - Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded."]
121 #[inline(always)]
122 pub fn txhrst(&self) -> TXHRST_R {
123 TXHRST_R::new(((self.bits >> 3) & 1) != 0)
124 }
125 #[doc = "Bit 4 - Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message."]
126 #[inline(always)]
127 pub fn rxmode(&self) -> RXMODE_R {
128 RXMODE_R::new(((self.bits >> 4) & 1) != 0)
129 }
130 #[doc = "Bit 5 - USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set."]
131 #[inline(always)]
132 pub fn phyrxen(&self) -> PHYRXEN_R {
133 PHYRXEN_R::new(((self.bits >> 5) & 1) != 0)
134 }
135 #[doc = "Bit 6 - CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach."]
136 #[inline(always)]
137 pub fn phyccsel(&self) -> PHYCCSEL_R {
138 PHYCCSEL_R::new(((self.bits >> 6) & 1) != 0)
139 }
140 #[doc = "Bits 7:8 - Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield."]
141 #[inline(always)]
142 pub fn anasubmode(&self) -> ANASUBMODE_R {
143 ANASUBMODE_R::new(((self.bits >> 7) & 3) as u8)
144 }
145 #[doc = "Bit 9 - Analog PHY operating mode The bit takes effect upon setting the UCPDx_STROBE bit of the SYS_CONFIG register. The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE\\[1:0\\]."]
146 #[inline(always)]
147 pub fn anamode(&self) -> ANAMODE_R {
148 ANAMODE_R::new(((self.bits >> 9) & 1) != 0)
149 }
150 #[doc = "Bits 10:11 - CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE\\[1:0\\]
151setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source."]
152 #[inline(always)]
153 pub fn ccenable(&self) -> CCENABLE_R {
154 CCENABLE_R::new(((self.bits >> 10) & 3) as u8)
155 }
156 #[doc = "Bit 13 - VCONN switch enable for CC1"]
157 #[inline(always)]
158 pub fn cc1vconnen(&self) -> CC1VCONNEN_R {
159 CC1VCONNEN_R::new(((self.bits >> 13) & 1) != 0)
160 }
161 #[doc = "Bit 14 - VCONN switch enable for CC2"]
162 #[inline(always)]
163 pub fn cc2vconnen(&self) -> CC2VCONNEN_R {
164 CC2VCONNEN_R::new(((self.bits >> 14) & 1) != 0)
165 }
166 #[doc = "Bit 15 - Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured."]
167 #[inline(always)]
168 pub fn dbatten(&self) -> DBATTEN_R {
169 DBATTEN_R::new(((self.bits >> 15) & 1) != 0)
170 }
171 #[doc = "Bit 16 - FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink."]
172 #[inline(always)]
173 pub fn frsrxen(&self) -> FRSRXEN_R {
174 FRSRXEN_R::new(((self.bits >> 16) & 1) != 0)
175 }
176 #[doc = "Bit 17 - FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0."]
177 #[inline(always)]
178 pub fn frstx(&self) -> FRSTX_R {
179 FRSTX_R::new(((self.bits >> 17) & 1) != 0)
180 }
181 #[doc = "Bit 18 - Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to \"USB Type-C ECN for Source VCONN Discharge\". The CCENABLE\\[1:0\\]
182bitfield must be set accordingly, too. Changing the bit value only takes effect upon setting the UCPDx_STROBE bit of the SYSCFG_CFGR1 register."]
183 #[inline(always)]
184 pub fn rdch(&self) -> RDCH_R {
185 RDCH_R::new(((self.bits >> 18) & 1) != 0)
186 }
187 #[doc = "Bit 20 - CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
188 #[inline(always)]
189 pub fn cc1tcdis(&self) -> CC1TCDIS_R {
190 CC1TCDIS_R::new(((self.bits >> 20) & 1) != 0)
191 }
192 #[doc = "Bit 21 - CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
193 #[inline(always)]
194 pub fn cc2tcdis(&self) -> CC2TCDIS_R {
195 CC2TCDIS_R::new(((self.bits >> 21) & 1) != 0)
196 }
197}
198impl W {
199 #[doc = "Bits 0:1 - Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the \"tBISTContMode\" delay), disable the peripheral (UCPDEN = 0)."]
200 #[inline(always)]
201 pub fn txmode(&mut self) -> TXMODE_W<0> {
202 TXMODE_W::new(self)
203 }
204 #[doc = "Bit 2 - Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded."]
205 #[inline(always)]
206 pub fn txsend(&mut self) -> TXSEND_W<2> {
207 TXSEND_W::new(self)
208 }
209 #[doc = "Bit 3 - Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded."]
210 #[inline(always)]
211 pub fn txhrst(&mut self) -> TXHRST_W<3> {
212 TXHRST_W::new(self)
213 }
214 #[doc = "Bit 4 - Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message."]
215 #[inline(always)]
216 pub fn rxmode(&mut self) -> RXMODE_W<4> {
217 RXMODE_W::new(self)
218 }
219 #[doc = "Bit 5 - USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set."]
220 #[inline(always)]
221 pub fn phyrxen(&mut self) -> PHYRXEN_W<5> {
222 PHYRXEN_W::new(self)
223 }
224 #[doc = "Bit 6 - CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach."]
225 #[inline(always)]
226 pub fn phyccsel(&mut self) -> PHYCCSEL_W<6> {
227 PHYCCSEL_W::new(self)
228 }
229 #[doc = "Bits 7:8 - Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield."]
230 #[inline(always)]
231 pub fn anasubmode(&mut self) -> ANASUBMODE_W<7> {
232 ANASUBMODE_W::new(self)
233 }
234 #[doc = "Bit 9 - Analog PHY operating mode The bit takes effect upon setting the UCPDx_STROBE bit of the SYS_CONFIG register. The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE\\[1:0\\]."]
235 #[inline(always)]
236 pub fn anamode(&mut self) -> ANAMODE_W<9> {
237 ANAMODE_W::new(self)
238 }
239 #[doc = "Bits 10:11 - CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE\\[1:0\\]
240setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source."]
241 #[inline(always)]
242 pub fn ccenable(&mut self) -> CCENABLE_W<10> {
243 CCENABLE_W::new(self)
244 }
245 #[doc = "Bit 13 - VCONN switch enable for CC1"]
246 #[inline(always)]
247 pub fn cc1vconnen(&mut self) -> CC1VCONNEN_W<13> {
248 CC1VCONNEN_W::new(self)
249 }
250 #[doc = "Bit 14 - VCONN switch enable for CC2"]
251 #[inline(always)]
252 pub fn cc2vconnen(&mut self) -> CC2VCONNEN_W<14> {
253 CC2VCONNEN_W::new(self)
254 }
255 #[doc = "Bit 15 - Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured."]
256 #[inline(always)]
257 pub fn dbatten(&mut self) -> DBATTEN_W<15> {
258 DBATTEN_W::new(self)
259 }
260 #[doc = "Bit 16 - FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink."]
261 #[inline(always)]
262 pub fn frsrxen(&mut self) -> FRSRXEN_W<16> {
263 FRSRXEN_W::new(self)
264 }
265 #[doc = "Bit 17 - FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0."]
266 #[inline(always)]
267 pub fn frstx(&mut self) -> FRSTX_W<17> {
268 FRSTX_W::new(self)
269 }
270 #[doc = "Bit 18 - Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to \"USB Type-C ECN for Source VCONN Discharge\". The CCENABLE\\[1:0\\]
271bitfield must be set accordingly, too. Changing the bit value only takes effect upon setting the UCPDx_STROBE bit of the SYSCFG_CFGR1 register."]
272 #[inline(always)]
273 pub fn rdch(&mut self) -> RDCH_W<18> {
274 RDCH_W::new(self)
275 }
276 #[doc = "Bit 20 - CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
277 #[inline(always)]
278 pub fn cc1tcdis(&mut self) -> CC1TCDIS_W<20> {
279 CC1TCDIS_W::new(self)
280 }
281 #[doc = "Bit 21 - CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
282 #[inline(always)]
283 pub fn cc2tcdis(&mut self) -> CC2TCDIS_W<21> {
284 CC2TCDIS_W::new(self)
285 }
286 #[doc = "Writes raw bits to the register."]
287 #[inline(always)]
288 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
289 self.0.bits(bits);
290 self
291 }
292}
293#[doc = "UCPD control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
294pub struct CR_SPEC;
295impl crate::RegisterSpec for CR_SPEC {
296 type Ux = u32;
297}
298#[doc = "`read()` method returns [cr::R](R) reader structure"]
299impl crate::Readable for CR_SPEC {
300 type Reader = R;
301}
302#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
303impl crate::Writable for CR_SPEC {
304 type Writer = W;
305}
306#[doc = "`reset()` method sets CR to value 0"]
307impl crate::Resettable for CR_SPEC {
308 #[inline(always)]
309 fn reset_value() -> Self::Ux {
310 0
311 }
312}