Module stm32g0::stm32g0c1::i2c1::i2c_cr2 [−][src]
Expand description
Control register 2
Structs
Field ADD10
reader - 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
Field ADD10
writer - 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
Field AUTOEND
reader - Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
Field AUTOEND
writer - Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
Field HEAD10R
reader - 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
Field HEAD10R
writer - 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
Control register 2
Field NACK
reader - NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing ’0â to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
Field NACK
writer - NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing ’0â to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
Field NBYTES
reader - Number of bytes The number of bytes to be transmitted/received is programmed there. This field is donât care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
Field NBYTES
writer - Number of bytes The number of bytes to be transmitted/received is programmed there. This field is donât care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
Field PECBYTE
reader - Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing ’0â to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Field PECBYTE
writer - Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing ’0â to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Register I2C_CR2
reader
Field RD_WRN
reader - Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
Field RD_WRN
writer - Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
Field RELOAD
reader - NBYTES reload mode This bit is set and cleared by software.
Field RELOAD
writer - NBYTES reload mode This bit is set and cleared by software.
Field SADD
reader - Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1]
should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8]
and SADD[0]
are don’t care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0]
should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
Field SADD
writer - Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1]
should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8]
and SADD[0]
are don’t care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0]
should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
Field START
reader - Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing ’1â to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing ’0â to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
Field START
writer - Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing ’1â to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing ’0â to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
Field STOP
reader - Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing ’0â to this bit has no effect.
Field STOP
writer - Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing ’0â to this bit has no effect.
Register I2C_CR2
writer
Enums
10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing ’0â to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing ’0â to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
NBYTES reload mode This bit is set and cleared by software.
Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing ’1â to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing ’0â to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing ’0â to this bit has no effect.