Struct stm32f7x5::dac::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub cr: CR, pub swtrigr: SWTRIGR, pub dhr12r1: DHR12R1, pub dhr12l1: DHR12L1, pub dhr8r1: DHR8R1, pub dhr12r2: DHR12R2, pub dhr12l2: DHR12L2, pub dhr8r2: DHR8R2, pub dhr12rd: DHR12RD, pub dhr12ld: DHR12LD, pub dhr8rd: DHR8RD, pub dor1: DOR1, pub dor2: DOR2, pub sr: SR, }
Register block
Fields
cr: CR
0x00 - control register
swtrigr: SWTRIGR
0x04 - software trigger register
dhr12r1: DHR12R1
0x08 - channel1 12-bit right-aligned data holding register
dhr12l1: DHR12L1
0x0c - channel1 12-bit left aligned data holding register
dhr8r1: DHR8R1
0x10 - channel1 8-bit right aligned data holding register
dhr12r2: DHR12R2
0x14 - channel2 12-bit right aligned data holding register
dhr12l2: DHR12L2
0x18 - channel2 12-bit left aligned data holding register
dhr8r2: DHR8R2
0x1c - channel2 8-bit right-aligned data holding register
dhr12rd: DHR12RD
0x20 - Dual DAC 12-bit right-aligned data holding register
dhr12ld: DHR12LD
0x24 - DUAL DAC 12-bit left aligned data holding register
dhr8rd: DHR8RD
0x28 - DUAL DAC 8-bit right aligned data holding register
dor1: DOR1
0x2c - channel1 data output register
dor2: DOR2
0x30 - channel2 data output register
sr: SR
0x34 - status register