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#[doc = "Reader of register CCR"] pub type R = crate::R<u32, super::CCR>; #[doc = "Writer for register CCR"] pub type W = crate::W<u32, super::CCR>; #[doc = "Register CCR `reset()`'s with value 0"] impl crate::ResetValue for super::CCR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `TSVREFE`"] pub type TSVREFE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSVREFE`"] pub struct TSVREFE_W<'a> { w: &'a mut W, } impl<'a> TSVREFE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); self.w } } #[doc = "Reader of field `VBATE`"] pub type VBATE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `VBATE`"] pub struct VBATE_W<'a> { w: &'a mut W, } impl<'a> VBATE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); self.w } } #[doc = "Reader of field `ADCPRE`"] pub type ADCPRE_R = crate::R<u8, u8>; #[doc = "Write proxy for field `ADCPRE`"] pub struct ADCPRE_W<'a> { w: &'a mut W, } impl<'a> ADCPRE_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16); self.w } } #[doc = "Reader of field `DMA`"] pub type DMA_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DMA`"] pub struct DMA_W<'a> { w: &'a mut W, } impl<'a> DMA_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14); self.w } } #[doc = "Reader of field `DDS`"] pub type DDS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DDS`"] pub struct DDS_W<'a> { w: &'a mut W, } impl<'a> DDS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); self.w } } #[doc = "Reader of field `DELAY`"] pub type DELAY_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DELAY`"] pub struct DELAY_W<'a> { w: &'a mut W, } impl<'a> DELAY_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); self.w } } #[doc = "Reader of field `MULT`"] pub type MULT_R = crate::R<u8, u8>; #[doc = "Write proxy for field `MULT`"] pub struct MULT_W<'a> { w: &'a mut W, } impl<'a> MULT_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f); self.w } } impl R { #[doc = "Bit 23 - Temperature sensor and VREFINT enable"] #[inline(always)] pub fn tsvrefe(&self) -> TSVREFE_R { TSVREFE_R::new(((self.bits >> 23) & 0x01) != 0) } #[doc = "Bit 22 - VBAT enable"] #[inline(always)] pub fn vbate(&self) -> VBATE_R { VBATE_R::new(((self.bits >> 22) & 0x01) != 0) } #[doc = "Bits 16:17 - ADC prescaler"] #[inline(always)] pub fn adcpre(&self) -> ADCPRE_R { ADCPRE_R::new(((self.bits >> 16) & 0x03) as u8) } #[doc = "Bits 14:15 - Direct memory access mode for multi ADC mode"] #[inline(always)] pub fn dma(&self) -> DMA_R { DMA_R::new(((self.bits >> 14) & 0x03) as u8) } #[doc = "Bit 13 - DMA disable selection for multi-ADC mode"] #[inline(always)] pub fn dds(&self) -> DDS_R { DDS_R::new(((self.bits >> 13) & 0x01) != 0) } #[doc = "Bits 8:11 - Delay between 2 sampling phases"] #[inline(always)] pub fn delay(&self) -> DELAY_R { DELAY_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bits 0:4 - Multi ADC mode selection"] #[inline(always)] pub fn mult(&self) -> MULT_R { MULT_R::new((self.bits & 0x1f) as u8) } } impl W { #[doc = "Bit 23 - Temperature sensor and VREFINT enable"] #[inline(always)] pub fn tsvrefe(&mut self) -> TSVREFE_W { TSVREFE_W { w: self } } #[doc = "Bit 22 - VBAT enable"] #[inline(always)] pub fn vbate(&mut self) -> VBATE_W { VBATE_W { w: self } } #[doc = "Bits 16:17 - ADC prescaler"] #[inline(always)] pub fn adcpre(&mut self) -> ADCPRE_W { ADCPRE_W { w: self } } #[doc = "Bits 14:15 - Direct memory access mode for multi ADC mode"] #[inline(always)] pub fn dma(&mut self) -> DMA_W { DMA_W { w: self } } #[doc = "Bit 13 - DMA disable selection for multi-ADC mode"] #[inline(always)] pub fn dds(&mut self) -> DDS_W { DDS_W { w: self } } #[doc = "Bits 8:11 - Delay between 2 sampling phases"] #[inline(always)] pub fn delay(&mut self) -> DELAY_W { DELAY_W { w: self } } #[doc = "Bits 0:4 - Multi ADC mode selection"] #[inline(always)] pub fn mult(&mut self) -> MULT_W { MULT_W { w: self } } }