Module stm32f7::stm32f7x3::fmc::sdcr

SDRAM Control Register 1

Structs

CAS_W	Write proxy for field CAS
MWID_W	Write proxy for field MWID
NB_W	Write proxy for field NB
NC_W	Write proxy for field NC
NR_W	Write proxy for field NR
RBURST_W	Write proxy for field RBURST
RPIPE_W	Write proxy for field RPIPE
SDCLK_W	Write proxy for field SDCLK
WP_W	Write proxy for field WP

Enums

CAS_A	CAS latency
MWID_A	Memory data bus width
NB_A	Number of internal banks
NC_A	Number of column address bits
NR_A	Number of row address bits
RBURST_A	Burst read
RPIPE_A	Read pipe
SDCLK_A	SDRAM clock configuration
WP_A	Write protection

Type Definitions

CAS_R	Reader of field CAS
MWID_R	Reader of field MWID
NB_R	Reader of field NB
NC_R	Reader of field NC
NR_R	Reader of field NR
R	Reader of register SDCR%s
RBURST_R	Reader of field RBURST
RPIPE_R	Reader of field RPIPE
SDCLK_R	Reader of field SDCLK
W	Writer for register SDCR%s
WP_R	Reader of field WP