Struct stm32f429x::dma2::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub lisr: Lisr, pub hisr: Hisr, pub lifcr: Lifcr, pub hifcr: Hifcr, pub s0cr: S0cr, pub s0ndtr: S0ndtr, pub s0par: S0par, pub s0m0ar: S0m0ar, pub s0m1ar: S0m1ar, pub s0fcr: S0fcr, pub s1cr: S1cr, pub s1ndtr: S1ndtr, pub s1par: S1par, pub s1m0ar: S1m0ar, pub s1m1ar: S1m1ar, pub s1fcr: S1fcr, pub s2cr: S2cr, pub s2ndtr: S2ndtr, pub s2par: S2par, pub s2m0ar: S2m0ar, pub s2m1ar: S2m1ar, pub s2fcr: S2fcr, pub s3cr: S3cr, pub s3ndtr: S3ndtr, pub s3par: S3par, pub s3m0ar: S3m0ar, pub s3m1ar: S3m1ar, pub s3fcr: S3fcr, pub s4cr: S4cr, pub s4ndtr: S4ndtr, pub s4par: S4par, pub s4m0ar: S4m0ar, pub s4m1ar: S4m1ar, pub s4fcr: S4fcr, pub s5cr: S5cr, pub s5ndtr: S5ndtr, pub s5par: S5par, pub s5m0ar: S5m0ar, pub s5m1ar: S5m1ar, pub s5fcr: S5fcr, pub s6cr: S6cr, pub s6ndtr: S6ndtr, pub s6par: S6par, pub s6m0ar: S6m0ar, pub s6m1ar: S6m1ar, pub s6fcr: S6fcr, pub s7cr: S7cr, pub s7ndtr: S7ndtr, pub s7par: S7par, pub s7m0ar: S7m0ar, pub s7m1ar: S7m1ar, pub s7fcr: S7fcr, }
Register block
Fields
lisr: Lisr
0x00 - low interrupt status register
hisr: Hisr
0x04 - high interrupt status register
lifcr: Lifcr
0x08 - low interrupt flag clear register
hifcr: Hifcr
0x0c - high interrupt flag clear register
s0cr: S0cr
0x10 - stream x configuration register
s0ndtr: S0ndtr
0x14 - stream x number of data register
s0par: S0par
0x18 - stream x peripheral address register
s0m0ar: S0m0ar
0x1c - stream x memory 0 address register
s0m1ar: S0m1ar
0x20 - stream x memory 1 address register
s0fcr: S0fcr
0x24 - stream x FIFO control register
s1cr: S1cr
0x28 - stream x configuration register
s1ndtr: S1ndtr
0x2c - stream x number of data register
s1par: S1par
0x30 - stream x peripheral address register
s1m0ar: S1m0ar
0x34 - stream x memory 0 address register
s1m1ar: S1m1ar
0x38 - stream x memory 1 address register
s1fcr: S1fcr
0x3c - stream x FIFO control register
s2cr: S2cr
0x40 - stream x configuration register
s2ndtr: S2ndtr
0x44 - stream x number of data register
s2par: S2par
0x48 - stream x peripheral address register
s2m0ar: S2m0ar
0x4c - stream x memory 0 address register
s2m1ar: S2m1ar
0x50 - stream x memory 1 address register
s2fcr: S2fcr
0x54 - stream x FIFO control register
s3cr: S3cr
0x58 - stream x configuration register
s3ndtr: S3ndtr
0x5c - stream x number of data register
s3par: S3par
0x60 - stream x peripheral address register
s3m0ar: S3m0ar
0x64 - stream x memory 0 address register
s3m1ar: S3m1ar
0x68 - stream x memory 1 address register
s3fcr: S3fcr
0x6c - stream x FIFO control register
s4cr: S4cr
0x70 - stream x configuration register
s4ndtr: S4ndtr
0x74 - stream x number of data register
s4par: S4par
0x78 - stream x peripheral address register
s4m0ar: S4m0ar
0x7c - stream x memory 0 address register
s4m1ar: S4m1ar
0x80 - stream x memory 1 address register
s4fcr: S4fcr
0x84 - stream x FIFO control register
s5cr: S5cr
0x88 - stream x configuration register
s5ndtr: S5ndtr
0x8c - stream x number of data register
s5par: S5par
0x90 - stream x peripheral address register
s5m0ar: S5m0ar
0x94 - stream x memory 0 address register
s5m1ar: S5m1ar
0x98 - stream x memory 1 address register
s5fcr: S5fcr
0x9c - stream x FIFO control register
s6cr: S6cr
0xa0 - stream x configuration register
s6ndtr: S6ndtr
0xa4 - stream x number of data register
s6par: S6par
0xa8 - stream x peripheral address register
s6m0ar: S6m0ar
0xac - stream x memory 0 address register
s6m1ar: S6m1ar
0xb0 - stream x memory 1 address register
s6fcr: S6fcr
0xb4 - stream x FIFO control register
s7cr: S7cr
0xb8 - stream x configuration register
s7ndtr: S7ndtr
0xbc - stream x number of data register
s7par: S7par
0xc0 - stream x peripheral address register
s7m0ar: S7m0ar
0xc4 - stream x memory 0 address register
s7m1ar: S7m1ar
0xc8 - stream x memory 1 address register
s7fcr: S7fcr
0xcc - stream x FIFO control register