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#[doc = "Reader of register CLKCR"] pub type R = crate::R<u32, super::CLKCR>; #[doc = "Writer for register CLKCR"] pub type W = crate::W<u32, super::CLKCR>; #[doc = "Register CLKCR `reset()`'s with value 0"] impl crate::ResetValue for super::CLKCR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `HWFC_EN`"] pub type HWFC_EN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `HWFC_EN`"] pub struct HWFC_EN_W<'a> { w: &'a mut W, } impl<'a> HWFC_EN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); self.w } } #[doc = "Reader of field `NEGEDGE`"] pub type NEGEDGE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `NEGEDGE`"] pub struct NEGEDGE_W<'a> { w: &'a mut W, } impl<'a> NEGEDGE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); self.w } } #[doc = "Reader of field `WIDBUS`"] pub type WIDBUS_R = crate::R<u8, u8>; #[doc = "Write proxy for field `WIDBUS`"] pub struct WIDBUS_W<'a> { w: &'a mut W, } impl<'a> WIDBUS_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 11)) | (((value as u32) & 0x03) << 11); self.w } } #[doc = "Reader of field `BYPASS`"] pub type BYPASS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `BYPASS`"] pub struct BYPASS_W<'a> { w: &'a mut W, } impl<'a> BYPASS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); self.w } } #[doc = "Reader of field `PWRSAV`"] pub type PWRSAV_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PWRSAV`"] pub struct PWRSAV_W<'a> { w: &'a mut W, } impl<'a> PWRSAV_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); self.w } } #[doc = "Reader of field `CLKEN`"] pub type CLKEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CLKEN`"] pub struct CLKEN_W<'a> { w: &'a mut W, } impl<'a> CLKEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Reader of field `CLKDIV`"] pub type CLKDIV_R = crate::R<u8, u8>; #[doc = "Write proxy for field `CLKDIV`"] pub struct CLKDIV_W<'a> { w: &'a mut W, } impl<'a> CLKDIV_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); self.w } } impl R { #[doc = "Bit 14 - HW Flow Control enable"] #[inline(always)] pub fn hwfc_en(&self) -> HWFC_EN_R { HWFC_EN_R::new(((self.bits >> 14) & 0x01) != 0) } #[doc = "Bit 13 - SDIO_CK dephasing selection bit"] #[inline(always)] pub fn negedge(&self) -> NEGEDGE_R { NEGEDGE_R::new(((self.bits >> 13) & 0x01) != 0) } #[doc = "Bits 11:12 - Wide bus mode enable bit"] #[inline(always)] pub fn widbus(&self) -> WIDBUS_R { WIDBUS_R::new(((self.bits >> 11) & 0x03) as u8) } #[doc = "Bit 10 - Clock divider bypass enable bit"] #[inline(always)] pub fn bypass(&self) -> BYPASS_R { BYPASS_R::new(((self.bits >> 10) & 0x01) != 0) } #[doc = "Bit 9 - Power saving configuration bit"] #[inline(always)] pub fn pwrsav(&self) -> PWRSAV_R { PWRSAV_R::new(((self.bits >> 9) & 0x01) != 0) } #[doc = "Bit 8 - Clock enable bit"] #[inline(always)] pub fn clken(&self) -> CLKEN_R { CLKEN_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bits 0:7 - Clock divide factor"] #[inline(always)] pub fn clkdiv(&self) -> CLKDIV_R { CLKDIV_R::new((self.bits & 0xff) as u8) } } impl W { #[doc = "Bit 14 - HW Flow Control enable"] #[inline(always)] pub fn hwfc_en(&mut self) -> HWFC_EN_W { HWFC_EN_W { w: self } } #[doc = "Bit 13 - SDIO_CK dephasing selection bit"] #[inline(always)] pub fn negedge(&mut self) -> NEGEDGE_W { NEGEDGE_W { w: self } } #[doc = "Bits 11:12 - Wide bus mode enable bit"] #[inline(always)] pub fn widbus(&mut self) -> WIDBUS_W { WIDBUS_W { w: self } } #[doc = "Bit 10 - Clock divider bypass enable bit"] #[inline(always)] pub fn bypass(&mut self) -> BYPASS_W { BYPASS_W { w: self } } #[doc = "Bit 9 - Power saving configuration bit"] #[inline(always)] pub fn pwrsav(&mut self) -> PWRSAV_W { PWRSAV_W { w: self } } #[doc = "Bit 8 - Clock enable bit"] #[inline(always)] pub fn clken(&mut self) -> CLKEN_W { CLKEN_W { w: self } } #[doc = "Bits 0:7 - Clock divide factor"] #[inline(always)] pub fn clkdiv(&mut self) -> CLKDIV_W { CLKDIV_W { w: self } } }